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88 Commits

Author SHA1 Message Date
Stanislav Shwartsman
d350c008e2
add softfloat3e library to Bochs to replace old softfloat2 (to get fp… (#259) 
…16 support)

with a lot of my updates, cleanups and extensions for x86 features like
denormal and/or undeflow/overflow handling

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Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2024-03-10 17:10:55 +02:00
Stanislav Shwartsman
3ff8fd5cd7 merge FCOMPP and FUCOMPP to same method to reduce code duplication 2024-02-20 07:22:58 +02:00
Shwartsman
6f4f217a08 implemented AMX_FP16 and aMX_COMPLEX, fixes for daz handling in AVX_NE_CONVERT FB16 
updated CHANGES
 2024-01-12 12:38:31 +02:00
Stanislav Shwartsman
3a02e85599
AMX support (#212) 2024-01-10 20:13:25 +02:00
Shwartsman
27d48ecb94 HandlersChaining Optimization: mark IN/OUT instructions as TraceEnd, they could have significant side effects like raising interrupts which have to be handled 
resolves issue #207
 2024-01-05 08:45:10 +02:00
Shwartsman
ddff78a16c style and disasm updates, no functional impact 2023-12-25 14:57:05 +02:00
Shwartsman
7c9bab8182 handle getexp methods though templates 2023-12-25 08:07:07 +02:00
Stanislav Shwartsman
662d8ec279 fix bug from previous commit 2023-12-24 15:04:31 +02:00
Shwartsman
19dbd7314b convert more instructions to template 2023-12-23 22:01:13 +02:00
Shwartsman
8e76c9b6bb move many SSE/AVX/AVX512 methods to template functions 2023-12-23 21:00:51 +02:00
Stanislav Shwartsman
54831068df
implement RDMSRLIST/WRMSRLIST instructions (+related VMX extensions) (#176) 2023-12-16 21:59:34 +02:00
Stanislav Shwartsman
2eccb25e8f x87: Implemented special behavior for 287-compatibility FSTP opcode: D9D8..D9DF - Behaves the same as FSTP but won't cause a stack underflow exception. 2023-12-07 12:56:02 +02:00
Stanislav Shwartsman
00e8e0bca0 implemented MOVDIR64B instruction and enabled in TigerLake model 2023-12-01 18:03:25 +02:00
Stanislav Shwartsman
2e89b9bcba
implemented WAITPKG instruction set (#150) 
still missing : UMWAIT/TPAUSE should set CF flag if it was using OS
deadline and woken up after deadline (i.e. not from monitored store)
also not clear in the spec: should UWAITX/TPAUSE always wait until
deadline due to 'while(tsc<deadline)' statement ?
+include small fixes for AMD's MONITORX/MWAITX
 2023-12-01 18:00:03 +02:00
Shwartsman
8dd9649389 fixed compilation for VMX=1 X86_64=1 
updated (c) for many files
 2023-11-28 10:36:56 +02:00
Stanislav Shwartsman
ad7a85d11a updates for SVM INVLPGA instruction 
- decoding and disasm
 - invalidate only pages pointed by RAX and not entire TLB
 2023-11-26 19:45:07 +02:00
Stanislav Shwartsman
280303d76c
initial code for UINTR implementation (#138) 
First step into implementing UINTR - User Level Interrupts ISA extension
To be continued

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Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2023-11-25 16:43:47 +02:00
Shwartsman
a7a443ab46 guard SVM functions with ifdef 2023-11-19 23:24:13 +02:00
Stanislav Shwartsman
f5b54a4d33
Implemented MOVDIRI instruction (#129) 
Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2023-11-11 20:30:12 +02:00
Stanislav Shwartsman
8594972389 final resolution for issue #2 : address VEXPAND* and VPSHUFBITQMB instructions 2023-11-09 19:15:32 +02:00
Stanislav Shwartsman
b78e93c9e3 optimize handling of allowed_to_run_FPU_MMX instructios common block 
now checked at decode and not at every instruction
simpler code and also 1% faster winXP boot time as bonus
other x87 and mmx heavy guests may benefit even more
 2023-11-08 06:48:53 +02:00
Stanislav Shwartsman
18deee022f
make CPU to use C++ template for implementation of CPU methods (#115) 
this allow to remove a lot of code from CPU common methods
 2023-10-30 06:57:16 +02:00
Shwartsman
02c4f85a89 implemented proper masked load for VPMOVSX/ZX instructions + bugfix 2023-10-20 20:13:29 +03:00
Stanislav Shwartsman
ffa64461ab
implementation of AVX-NE-CONVERT ISA (#89) 
Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2023-10-14 14:55:12 +03:00
Stanislav Shwartsman
dd7d4dbd82 implement SERIALIZE instruction 
enable CPUID reporting for all recently added ISA extensions
 2023-10-12 14:46:27 +03:00
Stanislav Shwartsman
4a309478f9
SHA512 instructions implemented (#88) 
Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2023-10-10 21:33:16 +03:00
Stanislav Shwartsman
3234e9b88e
implemented AVX VNNI INT16 ISA extension (#87) 
Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2023-10-10 20:22:07 +03:00
Stanislav Shwartsman
44eea71f37
implemented SM3 instructions (#84) 
add rol/ror methods to scalar_arith.h and use in more places

---------

Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2023-10-07 21:34:04 +03:00
Stanislav Shwartsman
0e4524f38f Implemented CMPccXADD instructions 2022-10-08 20:04:22 +03:00
Stanislav Shwartsman
a56144833a add support for AVX encoded VNNI INT8 extensions 2022-10-02 23:00:46 +03:00
Stanislav Shwartsman
3a20495db8 implemented WRMSRNS extension - Non Serializing version of WRMSR opcode 2022-10-02 22:16:02 +03:00
Stanislav Shwartsman
9f76eaacea implemented AVX IFMA instructions 2022-10-02 22:08:20 +03:00
Stanislav Shwartsman
c6050a99d1 implemented AVX encoded VNNI instructions published in recent SDM - not tested yet 2020-10-03 09:23:28 +00:00
Stanislav Shwartsman
81edc636d4 remove duplicate opcodes from decoder definitions 2020-03-28 14:36:27 +00:00
Stanislav Shwartsman
b686c8d423 add into ia_opcodes.def disasm field for every instruction 2020-03-28 14:23:54 +00:00
Stanislav Shwartsman
6879feebf5 SHA: SHA instructions in 128-bit memory operand require to be explicitly aligned 2019-12-27 14:24:43 +00:00
Stanislav Shwartsman
d6c3dcf033 revert for full vector read until figured out the right behavior for VPSHUFBITQMB 2019-12-24 20:08:33 +00:00
Stanislav Shwartsman
e38cca20be disable fault suppression for VPEXPAND* until fugured out how it should work in real life 2019-12-21 20:54:45 +00:00
Stanislav Shwartsman
c16816485e use optimized function for broadcastss 2019-12-21 20:20:33 +00:00
Stanislav Shwartsman
1a0237e9af make order in AVX512 broadcast handlers, extract them into separate file 2019-12-21 20:07:03 +00:00
Stanislav Shwartsman
11585e4982 AVX512: VPBROADCASTB/W/D/Q with GPR source are only reg/reg 2019-12-21 18:29:51 +00:00
Stanislav Shwartsman
afa3626eb3 AVX512: fixed compressed immediate size (and memory access size) for VPBROADCASTB_Eb form 2019-12-21 18:17:51 +00:00
Stanislav Shwartsman
0169605f79 seems like GFNI VGF2P8AFFINEQB and VGF2P8AFFINEINVQB do not have fault suppression 2019-12-21 18:01:58 +00:00
Stanislav Shwartsman
4ac2122f3a rename function to correct English, add broadcast and fault suppression support for EVEX encoded GFNI instructions 2019-12-21 16:12:06 +00:00
Stanislav Shwartsman
dd1ab303df rename function to correct English 2019-12-21 15:54:52 +00:00
Stanislav Shwartsman
723554d535 AVX512: Allow masked fault suppression for many AVX512 instructions - not all cases reviewed yet, more to come 2019-12-21 15:47:29 +00:00
Stanislav Shwartsman
74c73e5a76 AVX512: Allow masked fault suppression for many AVX512 instructions - not all cases reviewed yet, more to come 2019-12-20 15:34:14 +00:00
Stanislav Shwartsman
0e5d843597 AVX512: Allow masked fault suppression for many AVX512 instructions - not all cases reviewed yet, more to come 2019-12-20 14:58:56 +00:00
Stanislav Shwartsman
cff6a67adb AVX512: Allow masked fault suppression for many AVX512 instructions - not all cases reviewed yet, more to come 2019-12-20 14:57:42 +00:00
Stanislav Shwartsman
9fbf974e6b AVX512: Allow masked fault suppression for many AVX512 instructions - not all cases reviewed yet, more to come 2019-12-20 13:45:00 +00:00