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convert more instructions to template

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This commit is contained in:
Shwartsman 2023-12-23 21:51:24 +02:00
parent 8e76c9b6bb
commit 19dbd7314b
7 changed files with 287 additions and 364 deletions
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74
bochs/cpu/avx/avx512_fma.cc
View File

@ -37,80 +37,6 @@ extern float_status_t mxcsr_to_softfloat_status_word(bx_mxcsr_t mxcsr);
// AVX-512 FMA Instructions //
//////////////////////////////
#define EVEX_FMA_PACKED_SINGLE(HANDLER, func) \
void BX_CPP_AttrRegparmN(1) BX_CPU_C:: HANDLER (bxInstruction_c *i) \
{ \
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1()); \
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2()); \
BxPackedAvxRegister op3 = BX_READ_AVX_REG(i->src3()); \
unsigned mask = BX_READ_16BIT_OPMASK(i->opmask()); \
unsigned len = i->getVL(); \
\
float_status_t status = mxcsr_to_softfloat_status_word(MXCSR); \
softfloat_status_word_rc_override(status, i); \
\
for (unsigned n=0, tmp_mask = mask; n < len; n++, tmp_mask >>= 4) \
(func)(&op1.vmm128(n), &op2.vmm128(n), &op3.vmm128(n), status, tmp_mask); \
\
check_exceptionsSSE(get_exception_flags(status)); \
\
if (! i->isZeroMasking()) { \
for (unsigned n=0; n < len; n++, mask >>= 4) \
xmm_blendps(&BX_READ_AVX_REG_LANE(i->dst(), n), &op1.vmm128(n), mask); \
\
BX_CLEAR_AVX_REGZ(i->dst(), len); \
} \
else { \
BX_WRITE_AVX_REGZ(i->dst(), op1, len); \
} \
\
BX_NEXT_INSTR(i); \
}
EVEX_FMA_PACKED_SINGLE(VFMADDPS_MASK_VpsHpsWpsR, xmm_fmaddps_mask)
EVEX_FMA_PACKED_SINGLE(VFMADDSUBPS_MASK_VpsHpsWpsR, xmm_fmaddsubps_mask)
EVEX_FMA_PACKED_SINGLE(VFMSUBADDPS_MASK_VpsHpsWpsR, xmm_fmsubaddps_mask)
EVEX_FMA_PACKED_SINGLE(VFMSUBPS_MASK_VpsHpsWpsR, xmm_fmsubps_mask)
EVEX_FMA_PACKED_SINGLE(VFNMADDPS_MASK_VpsHpsWpsR, xmm_fnmaddps_mask)
EVEX_FMA_PACKED_SINGLE(VFNMSUBPS_MASK_VpsHpsWpsR, xmm_fnmsubps_mask)
#define EVEX_FMA_PACKED_DOUBLE(HANDLER, func) \
void BX_CPP_AttrRegparmN(1) BX_CPU_C:: HANDLER (bxInstruction_c *i) \
{ \
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1()); \
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2()); \
BxPackedAvxRegister op3 = BX_READ_AVX_REG(i->src3()); \
unsigned mask = BX_READ_8BIT_OPMASK(i->opmask()); \
unsigned len = i->getVL(); \
\
float_status_t status = mxcsr_to_softfloat_status_word(MXCSR); \
softfloat_status_word_rc_override(status, i); \
\
for (unsigned n=0, tmp_mask = mask; n < len; n++, tmp_mask >>= 2) \
(func)(&op1.vmm128(n), &op2.vmm128(n), &op3.vmm128(n), status, tmp_mask); \
\
check_exceptionsSSE(get_exception_flags(status)); \
\
if (! i->isZeroMasking()) { \
for (unsigned n=0; n < len; n++, mask >>= 2) \
xmm_blendpd(&BX_READ_AVX_REG_LANE(i->dst(), n), &op1.vmm128(n), mask); \
\
BX_CLEAR_AVX_REGZ(i->dst(), len); \
} \
else { \
BX_WRITE_AVX_REGZ(i->dst(), op1, len); \
} \
\
BX_NEXT_INSTR(i); \
}
EVEX_FMA_PACKED_DOUBLE(VFMADDPD_MASK_VpdHpdWpdR, xmm_fmaddpd_mask)
EVEX_FMA_PACKED_DOUBLE(VFMADDSUBPD_MASK_VpdHpdWpdR, xmm_fmaddsubpd_mask)
EVEX_FMA_PACKED_DOUBLE(VFMSUBADDPD_MASK_VpdHpdWpdR, xmm_fmsubaddpd_mask)
EVEX_FMA_PACKED_DOUBLE(VFMSUBPD_MASK_VpdHpdWpdR, xmm_fmsubpd_mask)
EVEX_FMA_PACKED_DOUBLE(VFNMADDPD_MASK_VpdHpdWpdR, xmm_fnmaddpd_mask)
EVEX_FMA_PACKED_DOUBLE(VFNMSUBPD_MASK_VpdHpdWpdR, xmm_fnmsubpd_mask)
#define EVEX_FMA_SCALAR_SINGLE(HANDLER, func) \
void BX_CPP_AttrRegparmN(1) BX_CPU_C:: HANDLER (bxInstruction_c *i) \
{ \

35
bochs/cpu/avx/avx_fma.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2011-2018 Stanislav Shwartsman
// Copyright (c) 2011-2023 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -36,39 +36,6 @@ extern float_status_t mxcsr_to_softfloat_status_word(bx_mxcsr_t mxcsr);
// AVX FMA Instructions //
//////////////////////////
#define AVX2_FMA_PACKED(HANDLER, func) \
void BX_CPP_AttrRegparmN(1) BX_CPU_C:: HANDLER (bxInstruction_c *i) \
{ \
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1()); \
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2()); \
BxPackedAvxRegister op3 = BX_READ_AVX_REG(i->src3()); \
unsigned len = i->getVL(); \
\
float_status_t status = mxcsr_to_softfloat_status_word(MXCSR); \
softfloat_status_word_rc_override(status, i); \
\
for (unsigned n=0; n < len; n++) \
(func)(&op1.vmm128(n), &op2.vmm128(n), &op3.vmm128(n), status); \
\
check_exceptionsSSE(get_exception_flags(status)); \
\
BX_WRITE_AVX_REGZ(i->dst(), op1, len); \
BX_NEXT_INSTR(i); \
}
AVX2_FMA_PACKED(VFMADDPD_VpdHpdWpdR, xmm_fmaddpd)
AVX2_FMA_PACKED(VFMADDPS_VpsHpsWpsR, xmm_fmaddps)
AVX2_FMA_PACKED(VFMADDSUBPD_VpdHpdWpdR, xmm_fmaddsubpd)
AVX2_FMA_PACKED(VFMADDSUBPS_VpsHpsWpsR, xmm_fmaddsubps)
AVX2_FMA_PACKED(VFMSUBADDPD_VpdHpdWpdR, xmm_fmsubaddpd)
AVX2_FMA_PACKED(VFMSUBADDPS_VpsHpsWpsR, xmm_fmsubaddps)
AVX2_FMA_PACKED(VFMSUBPD_VpdHpdWpdR, xmm_fmsubpd)
AVX2_FMA_PACKED(VFMSUBPS_VpsHpsWpsR, xmm_fmsubps)
AVX2_FMA_PACKED(VFNMADDPD_VpdHpdWpdR, xmm_fnmaddpd)
AVX2_FMA_PACKED(VFNMADDPS_VpsHpsWpsR, xmm_fnmaddps)
AVX2_FMA_PACKED(VFNMSUBPD_VpdHpdWpdR, xmm_fnmsubpd)
AVX2_FMA_PACKED(VFNMSUBPS_VpsHpsWpsR, xmm_fnmsubps)
#define AVX2_FMA_SCALAR_SINGLE(HANDLER, func) \
void BX_CPP_AttrRegparmN(1) BX_CPU_C:: HANDLER (bxInstruction_c *i) \
{ \

36
bochs/cpu/avx/avx_pfp.cc
View File

@ -129,42 +129,6 @@ float64_compare_method avx_compare64[32] = {
float64_true_signalling
};
/* Opcode: VEX.0F 51 (VEX.W ignore, VEX.VVV #UD) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VSQRTPS_VpsWpsR(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());
unsigned len = i->getVL();
float_status_t status = mxcsr_to_softfloat_status_word(MXCSR);
softfloat_status_word_rc_override(status, i);
for (unsigned n=0; n < len; n++) {
xmm_sqrtps(&op.vmm128(n), status);
}
check_exceptionsSSE(get_exception_flags(status));
BX_WRITE_AVX_REGZ(i->dst(), op, len);
BX_NEXT_INSTR(i);
}
/* Opcode: VEX.66.0F 51 (VEX.W ignore, VEX.VVV #UD) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VSQRTPD_VpdWpdR(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());
unsigned len = i->getVL();
float_status_t status = mxcsr_to_softfloat_status_word(MXCSR);
softfloat_status_word_rc_override(status, i);
for (unsigned n=0; n < len; n++) {
xmm_sqrtpd(&op.vmm128(n), status);
}
check_exceptionsSSE(get_exception_flags(status));
BX_WRITE_AVX_REGZ(i->dst(), op, len);
BX_NEXT_INSTR(i);
}
/* Opcode: VEX.NDS.F3.0F 51 (VEX.W ignore, VEX.L ignore) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VSQRTSS_VssHpsWssR(bxInstruction_c *i)
{

52
bochs/cpu/cpu.h
View File

@ -772,12 +772,16 @@ typedef struct {
#include "xmm.h"
struct float_status_t;
typedef void (*simd_xmm_shift)(BxPackedXmmRegister *opdst, Bit64u shift_64);
typedef void (*simd_xmm_1op)(BxPackedXmmRegister *opdst);
typedef void (*simd_xmm_2op)(BxPackedXmmRegister *opdst, const BxPackedXmmRegister *op2);
typedef void (*simd_xmm_3op)(BxPackedXmmRegister *opdst, const BxPackedXmmRegister *op1, const BxPackedXmmRegister *op2);
typedef void (*xmm_pfp_1op) (BxPackedXmmRegister *opdst, float_status_t &status);
typedef void (*xmm_pfp_1op_mask)(BxPackedXmmRegister *opdst, float_status_t &status, Bit32u mask);
typedef void (*xmm_pfp_2op) (BxPackedXmmRegister *opdst, const BxPackedXmmRegister *op1, float_status_t &status);
typedef void (*xmm_pfp_2op_mask)(BxPackedXmmRegister *opdst, const BxPackedXmmRegister *op1, float_status_t &status, Bit32u mask);
typedef void (*xmm_pfp_3op) (BxPackedXmmRegister *opdst, const BxPackedXmmRegister *op1, const BxPackedXmmRegister *op2, float_status_t &status);
@ -2301,6 +2305,8 @@ public: // for now...
template <simd_xmm_2op func>
BX_SMF void HANDLE_SSE_2OP(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
template <xmm_pfp_1op func>
BX_SMF void HANDLE_SSE_PFP_1OP(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
template <xmm_pfp_2op func>
BX_SMF void HANDLE_SSE_PFP_2OP(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -2329,7 +2335,6 @@ public: // for now...
BX_SMF void UCOMISS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void COMISS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void MOVMSKPS_GdUps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void SQRTPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void SQRTSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void RSQRTPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void RSQRTSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -2372,7 +2377,6 @@ public: // for now...
BX_SMF void UCOMISD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void COMISD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void MOVMSKPD_GdUpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void SQRTPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void SQRTSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void ADDSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void MULSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -2634,8 +2638,12 @@ public: // for now...
template <simd_xmm_3op func>
BX_SMF void HANDLE_AVX_3OP(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
template <xmm_pfp_1op func>
BX_SMF void HANDLE_AVX_PFP_1OP(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
template <xmm_pfp_2op func>
BX_SMF void HANDLE_AVX_PFP_2OP(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
template <xmm_pfp_3op func>
BX_SMF void HANDLE_AVX_PFP_3OP(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMOVSS_VssHpsWssR(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
BX_SMF void VMOVSD_VsdHpdWsdR(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
@ -2654,8 +2662,6 @@ public: // for now...
BX_SMF void VMOVMSKPS_GdUps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMOVMSKPD_GdUpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VPMOVMSKB_GdUdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VSQRTPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VSQRTPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VSQRTSS_VssHpsWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VSQRTSD_VsdHpdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VADDSS_VssHpsWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -2769,24 +2775,12 @@ public: // for now...
/* AVX2 */
/* AVX2 FMA */
BX_SMF void VFMADDPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFMADDPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFMADDSD_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFMADDSS_VpsHssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFMADDSUBPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFMADDSUBPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFMSUBADDPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFMSUBADDPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFMSUBPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFMSUBPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFMSUBSD_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFMSUBSS_VpsHssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFNMADDPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFNMADDPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFNMADDSD_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFNMADDSS_VpsHssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFNMSUBPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFNMSUBPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFNMSUBSD_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFNMSUBSS_VpsHssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
/* AVX2 FMA */
@ -3097,10 +3091,20 @@ public: // for now...
template <simd_xmm_shift func>
BX_SMF void HANDLE_AVX512_SHIFT_IMM_WORD_EL_MASK(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
template <xmm_pfp_1op_mask func>
BX_SMF void HANDLE_AVX512_MASK_PFP_1OP_SINGLE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
template <xmm_pfp_1op_mask func>
BX_SMF void HANDLE_AVX512_MASK_PFP_1OP_DOUBLE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
template <xmm_pfp_2op_mask func>
BX_SMF void HANDLE_AVX512_MASK_PFP_SINGLE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void HANDLE_AVX512_MASK_PFP_2OP_SINGLE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
template <xmm_pfp_2op_mask func>
BX_SMF void HANDLE_AVX512_MASK_PFP_DOUBLE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void HANDLE_AVX512_MASK_PFP_2OP_DOUBLE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
template <xmm_pfp_3op_mask func>
BX_SMF void HANDLE_AVX512_MASK_PFP_3OP_SINGLE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
template <xmm_pfp_3op_mask func>
BX_SMF void HANDLE_AVX512_MASK_PFP_3OP_DOUBLE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VADDSS_MASK_VssHpsWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VADDSD_MASK_VsdHpdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -3281,24 +3285,12 @@ public: // for now...
BX_SMF void VMOVSLDUP_MASK_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMOVDDUP_MASK_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFMADDPD_MASK_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFMADDPS_MASK_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFMADDSD_MASK_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFMADDSS_MASK_VpsHssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFMADDSUBPD_MASK_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFMADDSUBPS_MASK_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFMSUBADDPD_MASK_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFMSUBADDPS_MASK_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFMSUBPD_MASK_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFMSUBPS_MASK_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFMSUBSD_MASK_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFMSUBSS_MASK_VpsHssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFNMADDPD_MASK_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFNMADDPS_MASK_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFNMADDSD_MASK_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFNMADDSS_MASK_VpsHssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFNMSUBPD_MASK_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFNMSUBPS_MASK_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFNMSUBSD_MASK_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VFNMSUBSS_MASK_VpsHssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);

114
bochs/cpu/cpu_templates_pfp.h
View File

@ -24,6 +24,19 @@
extern float_status_t mxcsr_to_softfloat_status_word(bx_mxcsr_t mxcsr);
template <xmm_pfp_1op func>
void BX_CPP_AttrRegparmN(1) BX_CPU_C::HANDLE_SSE_PFP_1OP(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
float_status_t status = mxcsr_to_softfloat_status_word(MXCSR);
(func)(&op, status);
check_exceptionsSSE(get_exception_flags(status));
BX_WRITE_XMM_REG(i->dst(), op);
#endif
BX_NEXT_INSTR(i);
}
template <xmm_pfp_2op func>
void BX_CPP_AttrRegparmN(1) BX_CPU_C::HANDLE_SSE_PFP_2OP(bxInstruction_c *i)
{
@ -41,6 +54,24 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::HANDLE_SSE_PFP_2OP(bxInstruction_c *i)
#if BX_SUPPORT_AVX
template <xmm_pfp_1op func>
void BX_CPP_AttrRegparmN(1) BX_CPU_C::HANDLE_AVX_PFP_1OP(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());
unsigned len = i->getVL();
float_status_t status = mxcsr_to_softfloat_status_word(MXCSR);
softfloat_status_word_rc_override(status, i);
for (unsigned n=0; n < len; n++) {
(func)(&op.vmm128(n), status);
}
check_exceptionsSSE(get_exception_flags(status));
BX_WRITE_AVX_REGZ(i->dst(), op, len);
BX_NEXT_INSTR(i);
}
template <xmm_pfp_2op func>
void BX_CPP_AttrRegparmN(1) BX_CPU_C::HANDLE_AVX_PFP_2OP(bxInstruction_c *i)
{
@ -59,12 +90,31 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::HANDLE_AVX_PFP_2OP(bxInstruction_c *i)
BX_NEXT_INSTR(i);
}
template <xmm_pfp_3op func>
void BX_CPP_AttrRegparmN(1) BX_CPU_C::HANDLE_AVX_PFP_3OP(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2());
BxPackedAvxRegister op3 = BX_READ_AVX_REG(i->src3());
unsigned len = i->getVL();
float_status_t status = mxcsr_to_softfloat_status_word(MXCSR);
softfloat_status_word_rc_override(status, i);
for (unsigned n=0; n < len; n++)
(func)(&op1.vmm128(n), &op2.vmm128(n), &op3.vmm128(n), status);
check_exceptionsSSE(get_exception_flags(status));
BX_WRITE_AVX_REGZ(i->dst(), op1, len);
BX_NEXT_INSTR(i);
}
#if BX_SUPPORT_EVEX
#include "simd_int.h"
template <xmm_pfp_2op_mask func>
void BX_CPP_AttrRegparmN(1) BX_CPU_C::HANDLE_AVX512_MASK_PFP_SINGLE(bxInstruction_c *i)
void BX_CPP_AttrRegparmN(1) BX_CPU_C::HANDLE_AVX512_MASK_PFP_2OP_SINGLE(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1()), op2 = BX_READ_AVX_REG(i->src2());
unsigned mask = BX_READ_16BIT_OPMASK(i->opmask());
@ -92,7 +142,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::HANDLE_AVX512_MASK_PFP_SINGLE(bxInstructio
}
template <xmm_pfp_2op_mask func>
void BX_CPP_AttrRegparmN(1) BX_CPU_C::HANDLE_AVX512_MASK_PFP_DOUBLE(bxInstruction_c *i)
void BX_CPP_AttrRegparmN(1) BX_CPU_C::HANDLE_AVX512_MASK_PFP_2OP_DOUBLE(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1()), op2 = BX_READ_AVX_REG(i->src2());
unsigned mask = BX_READ_8BIT_OPMASK(i->opmask());
@ -119,6 +169,66 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::HANDLE_AVX512_MASK_PFP_DOUBLE(bxInstructio
BX_NEXT_INSTR(i);
}
template <xmm_pfp_3op_mask func>
void BX_CPP_AttrRegparmN(1) BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_SINGLE(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2());
BxPackedAvxRegister op3 = BX_READ_AVX_REG(i->src3());
unsigned mask = BX_READ_16BIT_OPMASK(i->opmask());
unsigned len = i->getVL();
float_status_t status = mxcsr_to_softfloat_status_word(MXCSR);
softfloat_status_word_rc_override(status, i);
for (unsigned n=0, tmp_mask = mask; n < len; n++, tmp_mask >>= 4)
(func)(&op1.vmm128(n), &op2.vmm128(n), &op3.vmm128(n), status, tmp_mask);
check_exceptionsSSE(get_exception_flags(status));
if (! i->isZeroMasking()) {
for (unsigned n=0; n < len; n++, mask >>= 4)
xmm_blendps(&BX_READ_AVX_REG_LANE(i->dst(), n), &op1.vmm128(n), mask);
BX_CLEAR_AVX_REGZ(i->dst(), len);
}
else {
BX_WRITE_AVX_REGZ(i->dst(), op1, len);
}
BX_NEXT_INSTR(i);
}
template <xmm_pfp_3op_mask func>
void BX_CPP_AttrRegparmN(1) BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_DOUBLE(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2());
BxPackedAvxRegister op3 = BX_READ_AVX_REG(i->src3());
unsigned mask = BX_READ_16BIT_OPMASK(i->opmask());
unsigned len = i->getVL();
float_status_t status = mxcsr_to_softfloat_status_word(MXCSR);
softfloat_status_word_rc_override(status, i);
for (unsigned n=0, tmp_mask = mask; n < len; n++, tmp_mask >>= 2)
(func)(&op1.vmm128(n), &op2.vmm128(n), &op3.vmm128(n), status, tmp_mask);
check_exceptionsSSE(get_exception_flags(status));
if (! i->isZeroMasking()) {
for (unsigned n=0; n < len; n++, mask >>= 2)
xmm_blendpd(&BX_READ_AVX_REG_LANE(i->dst(), n), &op1.vmm128(n), mask);
BX_CLEAR_AVX_REGZ(i->dst(), len);
}
else {
BX_WRITE_AVX_REGZ(i->dst(), op1, len);
}
BX_NEXT_INSTR(i);
}
#endif // BX_SUPPORT_EVEX
#endif // BX_SUPPORT_AVX

304
bochs/cpu/decoder/ia_opcodes.def
View File

@ -1117,8 +1117,8 @@ bx_define_opcode(BX_IA_MAXPD_VpdWpd, "maxpd", "maxpd", &BX_CPU_C::LOAD_Wdq, &BX_
bx_define_opcode(BX_IA_MAXSS_VssWss, "maxss", "maxss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::MAXSS_VssWssR, BX_ISA_SSE, OP_Vss, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_MAXSD_VsdWsd, "maxsd", "maxsd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::MAXSD_VsdWsdR, BX_ISA_SSE2, OP_Vsd, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_SQRTPS_VpsWps, "sqrtps", "sqrtps", &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SQRTPS_VpsWpsR, BX_ISA_SSE, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_SQRTPD_VpdWpd, "sqrtpd", "sqrtpd", &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SQRTPD_VpdWpdR, BX_ISA_SSE2, OP_Vpd, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_SQRTPS_VpsWps, "sqrtps", "sqrtps", &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::HANDLE_SSE_PFP_1OP<xmm_sqrtps>, BX_ISA_SSE, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_SQRTPD_VpdWpd, "sqrtpd", "sqrtpd", &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::HANDLE_SSE_PFP_1OP<xmm_sqrtpd>, BX_ISA_SSE2, OP_Vpd, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_SQRTSS_VssWss, "sqrtss", "sqrtss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::SQRTSS_VssWssR, BX_ISA_SSE, OP_Vss, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_SQRTSD_VsdWsd, "sqrtsd", "sqrtsd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::SQRTSD_VsdWsdR, BX_ISA_SSE2, OP_Vsd, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_SSE)
@ -1946,8 +1946,8 @@ bx_define_opcode(BX_IA_VMINPD_VpdHpdWpd, "vminpd", "vminpd", &BX_CPU_C::LOAD_Vec
bx_define_opcode(BX_IA_VMINSS_VssHpsWss, "vminss", "vminss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMINSS_VssHpsWssR, BX_ISA_AVX, OP_Vss, OP_Hps, OP_Wss, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMINSD_VsdHpdWsd, "vminsd", "vminsd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMINSD_VsdHpdWsdR, BX_ISA_AVX, OP_Vsd, OP_Hpd, OP_Wsd, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VSQRTPS_VpsWps, "vsqrtps", "vsqrtps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSQRTPS_VpsWpsR, BX_ISA_AVX, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VSQRTPD_VpdWpd, "vsqrtpd", "vsqrtpd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSQRTPD_VpdWpdR, BX_ISA_AVX, OP_Vpd, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VSQRTPS_VpsWps, "vsqrtps", "vsqrtps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_1OP<xmm_sqrtps>, BX_ISA_AVX, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VSQRTPD_VpdWpd, "vsqrtpd", "vsqrtpd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_1OP<xmm_sqrtpd>, BX_ISA_AVX, OP_Vpd, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VSQRTSS_VssHpsWss, "vsqrtss", "vsqrtss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VSQRTSS_VssHpsWssR, BX_ISA_AVX, OP_Vss, OP_Hps, OP_Wss, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VSQRTSD_VsdHpdWsd, "vsqrtsd", "vsqrtsd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VSQRTSD_VsdHpdWsdR, BX_ISA_AVX, OP_Vsd, OP_Hpd, OP_Wsd, OP_NONE, BX_PREPARE_AVX)
@ -2371,12 +2371,12 @@ bx_define_opcode(BX_IA_VPSRAVD_VdqHdqWdq, "vpsravd", "vpsravd", &BX_CPU_C::LOAD_
// AVX1/AVX2
// AVX2 FMA
bx_define_opcode(BX_IA_VFMADD132PS_VpsHpsWps, "vfmadd132ps", "vfmadd132ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPS_VpsHpsWpsR, BX_ISA_AVX_FMA, OP_Vps, OP_Vps, OP_Wps, OP_Hps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADD132PD_VpdHpdWpd, "vfmadd132pd", "vfmadd132pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPD_VpdHpdWpdR, BX_ISA_AVX_FMA, OP_Vpd, OP_Vpd, OP_Wpd, OP_Hpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADD213PS_VpsHpsWps, "vfmadd213ps", "vfmadd213ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPS_VpsHpsWpsR, BX_ISA_AVX_FMA, OP_Vps, OP_Hps, OP_Vps, OP_Wps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADD213PD_VpdHpdWpd, "vfmadd213pd", "vfmadd213pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPD_VpdHpdWpdR, BX_ISA_AVX_FMA, OP_Vpd, OP_Hpd, OP_Vpd, OP_Wpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADD231PS_VpsHpsWps, "vfmadd231ps", "vfmadd231ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPS_VpsHpsWpsR, BX_ISA_AVX_FMA, OP_Vps, OP_Hps, OP_Wps, OP_Vps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADD231PD_VpdHpdWpd, "vfmadd231pd", "vfmadd231pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPD_VpdHpdWpdR, BX_ISA_AVX_FMA, OP_Vpd, OP_Hpd, OP_Wpd, OP_Vpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADD132PS_VpsHpsWps, "vfmadd132ps", "vfmadd132ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddps>, BX_ISA_AVX_FMA, OP_Vps, OP_Vps, OP_Wps, OP_Hps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADD132PD_VpdHpdWpd, "vfmadd132pd", "vfmadd132pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddpd>, BX_ISA_AVX_FMA, OP_Vpd, OP_Vpd, OP_Wpd, OP_Hpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADD213PS_VpsHpsWps, "vfmadd213ps", "vfmadd213ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddps>, BX_ISA_AVX_FMA, OP_Vps, OP_Hps, OP_Vps, OP_Wps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADD213PD_VpdHpdWpd, "vfmadd213pd", "vfmadd213pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddpd>, BX_ISA_AVX_FMA, OP_Vpd, OP_Hpd, OP_Vpd, OP_Wpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADD231PS_VpsHpsWps, "vfmadd231ps", "vfmadd231ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddps>, BX_ISA_AVX_FMA, OP_Vps, OP_Hps, OP_Wps, OP_Vps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADD231PD_VpdHpdWpd, "vfmadd231pd", "vfmadd231pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddpd>, BX_ISA_AVX_FMA, OP_Vpd, OP_Hpd, OP_Wpd, OP_Vpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADD132SS_VpsHssWss, "vfmadd132ss", "vfmadd132ss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMADDSS_VpsHssWssR, BX_ISA_AVX_FMA, OP_Vps, OP_Vps, OP_Wss, OP_Hss, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADD132SD_VpdHsdWsd, "vfmadd132sd", "vfmadd132sd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMADDSD_VpdHsdWsdR, BX_ISA_AVX_FMA, OP_Vpd, OP_Vpd, OP_Wsd, OP_Hsd, BX_PREPARE_AVX)
@ -2385,26 +2385,26 @@ bx_define_opcode(BX_IA_VFMADD213SD_VpdHsdWsd, "vfmadd213sd", "vfmadd213sd", &BX_
bx_define_opcode(BX_IA_VFMADD231SS_VpsHssWss, "vfmadd231ss", "vfmadd231ss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMADDSS_VpsHssWssR, BX_ISA_AVX_FMA, OP_Vps, OP_Hss, OP_Wss, OP_Vss, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADD231SD_VpdHsdWsd, "vfmadd231sd", "vfmadd231sd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMADDSD_VpdHsdWsdR, BX_ISA_AVX_FMA, OP_Vpd, OP_Hsd, OP_Wsd, OP_Vsd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDSUB132PS_VpsHpsWps, "vfmaddsub132ps", "vfmaddsub132ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPS_VpsHpsWpsR, BX_ISA_AVX_FMA, OP_Vps, OP_Vps, OP_Wps, OP_Hps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDSUB132PD_VpdHpdWpd, "vfmaddsub132pd", "vfmaddsub132pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPD_VpdHpdWpdR, BX_ISA_AVX_FMA, OP_Vpd, OP_Vpd, OP_Wpd, OP_Hpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDSUB213PS_VpsHpsWps, "vfmaddsub213ps", "vfmaddsub213ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPS_VpsHpsWpsR, BX_ISA_AVX_FMA, OP_Vps, OP_Hps, OP_Vps, OP_Wps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDSUB213PD_VpdHpdWpd, "vfmaddsub213pd", "vfmaddsub213pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPD_VpdHpdWpdR, BX_ISA_AVX_FMA, OP_Vpd, OP_Hpd, OP_Vpd, OP_Wpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDSUB231PS_VpsHpsWps, "vfmaddsub231ps", "vfmaddsub231ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPS_VpsHpsWpsR, BX_ISA_AVX_FMA, OP_Vps, OP_Hps, OP_Wps, OP_Vps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDSUB231PD_VpdHpdWpd, "vfmaddsub231pd", "vfmaddsub231pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPD_VpdHpdWpdR, BX_ISA_AVX_FMA, OP_Vpd, OP_Hpd, OP_Wpd, OP_Vpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDSUB132PS_VpsHpsWps, "vfmaddsub132ps", "vfmaddsub132ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddsubps>, BX_ISA_AVX_FMA, OP_Vps, OP_Vps, OP_Wps, OP_Hps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDSUB132PD_VpdHpdWpd, "vfmaddsub132pd", "vfmaddsub132pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddsubpd>, BX_ISA_AVX_FMA, OP_Vpd, OP_Vpd, OP_Wpd, OP_Hpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDSUB213PS_VpsHpsWps, "vfmaddsub213ps", "vfmaddsub213ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddsubps>, BX_ISA_AVX_FMA, OP_Vps, OP_Hps, OP_Vps, OP_Wps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDSUB213PD_VpdHpdWpd, "vfmaddsub213pd", "vfmaddsub213pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddsubpd>, BX_ISA_AVX_FMA, OP_Vpd, OP_Hpd, OP_Vpd, OP_Wpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDSUB231PS_VpsHpsWps, "vfmaddsub231ps", "vfmaddsub231ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddsubps>, BX_ISA_AVX_FMA, OP_Vps, OP_Hps, OP_Wps, OP_Vps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDSUB231PD_VpdHpdWpd, "vfmaddsub231pd", "vfmaddsub231pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddsubpd>, BX_ISA_AVX_FMA, OP_Vpd, OP_Hpd, OP_Wpd, OP_Vpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBADD132PS_VpsHpsWps, "vfmsubadd132ps", "vfmsubadd132ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPS_VpsHpsWpsR, BX_ISA_AVX_FMA, OP_Vps, OP_Vps, OP_Wps, OP_Hps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBADD132PD_VpdHpdWpd, "vfmsubadd132pd", "vfmsubadd132pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPD_VpdHpdWpdR, BX_ISA_AVX_FMA, OP_Vpd, OP_Vpd, OP_Wpd, OP_Hpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBADD213PS_VpsHpsWps, "vfmsubadd213ps", "vfmsubadd213ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPS_VpsHpsWpsR, BX_ISA_AVX_FMA, OP_Vps, OP_Hps, OP_Vps, OP_Wps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBADD213PD_VpdHpdWpd, "vfmsubadd213pd", "vfmsubadd213pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPD_VpdHpdWpdR, BX_ISA_AVX_FMA, OP_Vpd, OP_Hpd, OP_Vpd, OP_Wpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBADD231PS_VpsHpsWps, "vfmsubadd231ps", "vfmsubadd231ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPS_VpsHpsWpsR, BX_ISA_AVX_FMA, OP_Vps, OP_Hps, OP_Wps, OP_Vps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBADD231PD_VpdHpdWpd, "vfmsubadd231pd", "vfmsubadd231pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPD_VpdHpdWpdR, BX_ISA_AVX_FMA, OP_Vpd, OP_Hpd, OP_Wpd, OP_Vpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBADD132PS_VpsHpsWps, "vfmsubadd132ps", "vfmsubadd132ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubaddps>, BX_ISA_AVX_FMA, OP_Vps, OP_Vps, OP_Wps, OP_Hps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBADD132PD_VpdHpdWpd, "vfmsubadd132pd", "vfmsubadd132pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubaddpd>, BX_ISA_AVX_FMA, OP_Vpd, OP_Vpd, OP_Wpd, OP_Hpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBADD213PS_VpsHpsWps, "vfmsubadd213ps", "vfmsubadd213ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubaddps>, BX_ISA_AVX_FMA, OP_Vps, OP_Hps, OP_Vps, OP_Wps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBADD213PD_VpdHpdWpd, "vfmsubadd213pd", "vfmsubadd213pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubaddpd>, BX_ISA_AVX_FMA, OP_Vpd, OP_Hpd, OP_Vpd, OP_Wpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBADD231PS_VpsHpsWps, "vfmsubadd231ps", "vfmsubadd231ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubaddps>, BX_ISA_AVX_FMA, OP_Vps, OP_Hps, OP_Wps, OP_Vps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBADD231PD_VpdHpdWpd, "vfmsubadd231pd", "vfmsubadd231pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubaddpd>, BX_ISA_AVX_FMA, OP_Vpd, OP_Hpd, OP_Wpd, OP_Vpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUB132PS_VpsHpsWps, "vfmsub132ps", "vfmsub132ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPS_VpsHpsWpsR, BX_ISA_AVX_FMA, OP_Vps, OP_Vps, OP_Wps, OP_Hps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUB132PD_VpdHpdWpd, "vfmsub132pd", "vfmsub132pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPD_VpdHpdWpdR, BX_ISA_AVX_FMA, OP_Vpd, OP_Vpd, OP_Wpd, OP_Hpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUB213PS_VpsHpsWps, "vfmsub213ps", "vfmsub213ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPS_VpsHpsWpsR, BX_ISA_AVX_FMA, OP_Vps, OP_Hps, OP_Vps, OP_Wps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUB213PD_VpdHpdWpd, "vfmsub213pd", "vfmsub213pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPD_VpdHpdWpdR, BX_ISA_AVX_FMA, OP_Vpd, OP_Hpd, OP_Vpd, OP_Wpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUB231PS_VpsHpsWps, "vfmsub231ps", "vfmsub231ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPS_VpsHpsWpsR, BX_ISA_AVX_FMA, OP_Vps, OP_Hps, OP_Wps, OP_Vps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUB231PD_VpdHpdWpd, "vfmsub231pd", "vfmsub231pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPD_VpdHpdWpdR, BX_ISA_AVX_FMA, OP_Vpd, OP_Hpd, OP_Wpd, OP_Vpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUB132PS_VpsHpsWps, "vfmsub132ps", "vfmsub132ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubps>, BX_ISA_AVX_FMA, OP_Vps, OP_Vps, OP_Wps, OP_Hps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUB132PD_VpdHpdWpd, "vfmsub132pd", "vfmsub132pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubpd>, BX_ISA_AVX_FMA, OP_Vpd, OP_Vpd, OP_Wpd, OP_Hpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUB213PS_VpsHpsWps, "vfmsub213ps", "vfmsub213ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubps>, BX_ISA_AVX_FMA, OP_Vps, OP_Hps, OP_Vps, OP_Wps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUB213PD_VpdHpdWpd, "vfmsub213pd", "vfmsub213pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubpd>, BX_ISA_AVX_FMA, OP_Vpd, OP_Hpd, OP_Vpd, OP_Wpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUB231PS_VpsHpsWps, "vfmsub231ps", "vfmsub231ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubps>, BX_ISA_AVX_FMA, OP_Vps, OP_Hps, OP_Wps, OP_Vps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUB231PD_VpdHpdWpd, "vfmsub231pd", "vfmsub231pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubpd>, BX_ISA_AVX_FMA, OP_Vpd, OP_Hpd, OP_Wpd, OP_Vpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUB132SS_VpsHssWss, "vfmsub132ss", "vfmsub132ss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMSUBSS_VpsHssWssR, BX_ISA_AVX_FMA, OP_Vps, OP_Vps, OP_Wss, OP_Hss, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUB132SD_VpdHsdWsd, "vfmsub132sd", "vfmsub132sd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMSUBSD_VpdHsdWsdR, BX_ISA_AVX_FMA, OP_Vpd, OP_Vpd, OP_Wsd, OP_Hsd, BX_PREPARE_AVX)
@ -2413,12 +2413,12 @@ bx_define_opcode(BX_IA_VFMSUB213SD_VpdHsdWsd, "vfmsub213sd", "vfmsub213sd", &BX_
bx_define_opcode(BX_IA_VFMSUB231SS_VpsHssWss, "vfmsub231ss", "vfmsub231ss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMSUBSS_VpsHssWssR, BX_ISA_AVX_FMA, OP_Vps, OP_Hss, OP_Wss, OP_Vss, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUB231SD_VpdHsdWsd, "vfmsub231sd", "vfmsub231sd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMSUBSD_VpdHsdWsdR, BX_ISA_AVX_FMA, OP_Vpd, OP_Hsd, OP_Wsd, OP_Vsd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMADD132PS_VpsHpsWps, "vfnmadd132ps", "vfnmadd132ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPS_VpsHpsWpsR, BX_ISA_AVX_FMA, OP_Vps, OP_Vps, OP_Wps, OP_Hps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMADD132PD_VpdHpdWpd, "vfnmadd132pd", "vfnmadd132pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPD_VpdHpdWpdR, BX_ISA_AVX_FMA, OP_Vpd, OP_Vpd, OP_Wpd, OP_Hpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMADD213PS_VpsHpsWps, "vfnmadd213ps", "vfnmadd213ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPS_VpsHpsWpsR, BX_ISA_AVX_FMA, OP_Vps, OP_Hps, OP_Vps, OP_Wps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMADD213PD_VpdHpdWpd, "vfnmadd213pd", "vfnmadd213pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPD_VpdHpdWpdR, BX_ISA_AVX_FMA, OP_Vpd, OP_Hpd, OP_Vpd, OP_Wpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMADD231PS_VpsHpsWps, "vfnmadd231ps", "vfnmadd231ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPS_VpsHpsWpsR, BX_ISA_AVX_FMA, OP_Vps, OP_Hps, OP_Wps, OP_Vps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMADD231PD_VpdHpdWpd, "vfnmadd231pd", "vfnmadd231pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPD_VpdHpdWpdR, BX_ISA_AVX_FMA, OP_Vpd, OP_Hpd, OP_Wpd, OP_Vpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMADD132PS_VpsHpsWps, "vfnmadd132ps", "vfnmadd132ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmaddps>, BX_ISA_AVX_FMA, OP_Vps, OP_Vps, OP_Wps, OP_Hps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMADD132PD_VpdHpdWpd, "vfnmadd132pd", "vfnmadd132pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmaddpd>, BX_ISA_AVX_FMA, OP_Vpd, OP_Vpd, OP_Wpd, OP_Hpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMADD213PS_VpsHpsWps, "vfnmadd213ps", "vfnmadd213ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmaddps>, BX_ISA_AVX_FMA, OP_Vps, OP_Hps, OP_Vps, OP_Wps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMADD213PD_VpdHpdWpd, "vfnmadd213pd", "vfnmadd213pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmaddpd>, BX_ISA_AVX_FMA, OP_Vpd, OP_Hpd, OP_Vpd, OP_Wpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMADD231PS_VpsHpsWps, "vfnmadd231ps", "vfnmadd231ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmaddps>, BX_ISA_AVX_FMA, OP_Vps, OP_Hps, OP_Wps, OP_Vps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMADD231PD_VpdHpdWpd, "vfnmadd231pd", "vfnmadd231pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmaddpd>, BX_ISA_AVX_FMA, OP_Vpd, OP_Hpd, OP_Wpd, OP_Vpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMADD132SS_VpsHssWss, "vfnmadd132ss", "vfnmadd132ss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMADDSS_VpsHssWssR, BX_ISA_AVX_FMA, OP_Vps, OP_Vps, OP_Wss, OP_Hss, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMADD132SD_VpdHsdWsd, "vfnmadd132sd", "vfnmadd132sd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMADDSD_VpdHsdWsdR, BX_ISA_AVX_FMA, OP_Vpd, OP_Vpd, OP_Wsd, OP_Hsd, BX_PREPARE_AVX)
@ -2427,12 +2427,12 @@ bx_define_opcode(BX_IA_VFNMADD213SD_VpdHsdWsd, "vfnmadd213sd", "vfnmadd213sd", &
bx_define_opcode(BX_IA_VFNMADD231SS_VpsHssWss, "vfnmadd231ss", "vfnmadd231ss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMADDSS_VpsHssWssR, BX_ISA_AVX_FMA, OP_Vps, OP_Hss, OP_Wss, OP_Vss, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMADD231SD_VpdHsdWsd, "vfnmadd231sd", "vfnmadd231sd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMADDSD_VpdHsdWsdR, BX_ISA_AVX_FMA, OP_Vpd, OP_Hsd, OP_Wsd, OP_Vsd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMSUB132PS_VpsHpsWps, "vfnmsub132ps", "vfnmsub132ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPS_VpsHpsWpsR, BX_ISA_AVX_FMA, OP_Vps, OP_Vps, OP_Wps, OP_Hps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMSUB132PD_VpdHpdWpd, "vfnmsub132pd", "vfnmsub132pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPD_VpdHpdWpdR, BX_ISA_AVX_FMA, OP_Vpd, OP_Vpd, OP_Wpd, OP_Hpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMSUB213PS_VpsHpsWps, "vfnmsub213ps", "vfnmsub213ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPS_VpsHpsWpsR, BX_ISA_AVX_FMA, OP_Vps, OP_Hps, OP_Vps, OP_Wps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMSUB213PD_VpdHpdWpd, "vfnmsub213pd", "vfnmsub213pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPD_VpdHpdWpdR, BX_ISA_AVX_FMA, OP_Vpd, OP_Hpd, OP_Vpd, OP_Wpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMSUB231PS_VpsHpsWps, "vfnmsub231ps", "vfnmsub231ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPS_VpsHpsWpsR, BX_ISA_AVX_FMA, OP_Vps, OP_Hps, OP_Wps, OP_Vps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMSUB231PD_VpdHpdWpd, "vfnmsub231pd", "vfnmsub231pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPD_VpdHpdWpdR, BX_ISA_AVX_FMA, OP_Vpd, OP_Hpd, OP_Wpd, OP_Vpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMSUB132PS_VpsHpsWps, "vfnmsub132ps", "vfnmsub132ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmsubps>, BX_ISA_AVX_FMA, OP_Vps, OP_Vps, OP_Wps, OP_Hps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMSUB132PD_VpdHpdWpd, "vfnmsub132pd", "vfnmsub132pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmsubpd>, BX_ISA_AVX_FMA, OP_Vpd, OP_Vpd, OP_Wpd, OP_Hpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMSUB213PS_VpsHpsWps, "vfnmsub213ps", "vfnmsub213ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmsubps>, BX_ISA_AVX_FMA, OP_Vps, OP_Hps, OP_Vps, OP_Wps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMSUB213PD_VpdHpdWpd, "vfnmsub213pd", "vfnmsub213pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmsubpd>, BX_ISA_AVX_FMA, OP_Vpd, OP_Hpd, OP_Vpd, OP_Wpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMSUB231PS_VpsHpsWps, "vfnmsub231ps", "vfnmsub231ps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmsubps>, BX_ISA_AVX_FMA, OP_Vps, OP_Hps, OP_Wps, OP_Vps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMSUB231PD_VpdHpdWpd, "vfnmsub231pd", "vfnmsub231pd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmsubpd>, BX_ISA_AVX_FMA, OP_Vpd, OP_Hpd, OP_Wpd, OP_Vpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMSUB132SS_VpsHssWss, "vfnmsub132ss", "vfnmsub132ss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMSUBSS_VpsHssWssR, BX_ISA_AVX_FMA, OP_Vps, OP_Vps, OP_Wps, OP_Hps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMSUB132SD_VpdHsdWsd, "vfnmsub132sd", "vfnmsub132sd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMSUBSD_VpdHsdWsdR, BX_ISA_AVX_FMA, OP_Vpd, OP_Vpd, OP_Wpd, OP_Hpd, BX_PREPARE_AVX)
@ -2550,42 +2550,42 @@ bx_define_opcode(BX_IA_CMPZXADD_EqGqBq, "cmpzxadd", "cmpzxaddq", &BX_CPU_C::CMPZ
// CMPccXADD
// FMA4 (AMD)
bx_define_opcode(BX_IA_VFMADDSUBPS_VpsHpsVIbWps, "vfmaddsubps", "vfmaddsubps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPS_VpsHpsWpsR, BX_ISA_FMA4, OP_Vps, OP_Hps, OP_VIb, OP_Wps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDSUBPS_VpsHpsWpsVIb, "vfmaddsubps", "vfmaddsubps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPS_VpsHpsWpsR, BX_ISA_FMA4, OP_Vps, OP_Hps, OP_Wps, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDSUBPD_VpdHpdVIbWpd, "vfmaddsubpd", "vfmaddsubpd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPD_VpdHpdWpdR, BX_ISA_FMA4, OP_Vpd, OP_Hpd, OP_VIb, OP_Wpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDSUBPD_VpdHpdWpdVIb, "vfmaddsubpd", "vfmaddsubpd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDSUBPD_VpdHpdWpdR, BX_ISA_FMA4, OP_Vpd, OP_Hpd, OP_Wpd, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBADDPS_VpsHpsVIbWps, "vfmsubaddps", "vfmsubaddps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPS_VpsHpsWpsR, BX_ISA_FMA4, OP_Vps, OP_Hps, OP_VIb, OP_Wps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBADDPS_VpsHpsWpsVIb, "vfmsubaddps", "vfmsubaddps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPS_VpsHpsWpsR, BX_ISA_FMA4, OP_Vps, OP_Hps, OP_Wps, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBADDPD_VpdHpdVIbWpd, "vfmsubaddpd", "vfmsubaddpd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPD_VpdHpdWpdR, BX_ISA_FMA4, OP_Vpd, OP_Hpd, OP_VIb, OP_Wpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBADDPD_VpdHpdWpdVIb, "vfmsubaddpd", "vfmsubaddpd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBADDPD_VpdHpdWpdR, BX_ISA_FMA4, OP_Vpd, OP_Hpd, OP_Wpd, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDPS_VpsHpsVIbWps, "vfmaddps", "vfmaddps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPS_VpsHpsWpsR, BX_ISA_FMA4, OP_Vps, OP_Hps, OP_VIb, OP_Wps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDPS_VpsHpsWpsVIb, "vfmaddps", "vfmaddps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPS_VpsHpsWpsR, BX_ISA_FMA4, OP_Vps, OP_Hps, OP_Wps, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDPD_VpdHpdVIbWpd, "vfmaddpd", "vfmaddpd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPD_VpdHpdWpdR, BX_ISA_FMA4, OP_Vpd, OP_Hpd, OP_VIb, OP_Wpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDPD_VpdHpdWpdVIb, "vfmaddpd", "vfmaddpd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPD_VpdHpdWpdR, BX_ISA_FMA4, OP_Vpd, OP_Hpd, OP_Wpd, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDSUBPS_VpsHpsVIbWps, "vfmaddsubps", "vfmaddsubps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddsubps>, BX_ISA_FMA4, OP_Vps, OP_Hps, OP_VIb, OP_Wps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDSUBPS_VpsHpsWpsVIb, "vfmaddsubps", "vfmaddsubps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddsubps>, BX_ISA_FMA4, OP_Vps, OP_Hps, OP_Wps, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDSUBPD_VpdHpdVIbWpd, "vfmaddsubpd", "vfmaddsubpd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddsubpd>, BX_ISA_FMA4, OP_Vpd, OP_Hpd, OP_VIb, OP_Wpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDSUBPD_VpdHpdWpdVIb, "vfmaddsubpd", "vfmaddsubpd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddsubpd>, BX_ISA_FMA4, OP_Vpd, OP_Hpd, OP_Wpd, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBADDPS_VpsHpsVIbWps, "vfmsubaddps", "vfmsubaddps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubaddps>, BX_ISA_FMA4, OP_Vps, OP_Hps, OP_VIb, OP_Wps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBADDPS_VpsHpsWpsVIb, "vfmsubaddps", "vfmsubaddps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubaddps>, BX_ISA_FMA4, OP_Vps, OP_Hps, OP_Wps, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBADDPD_VpdHpdVIbWpd, "vfmsubaddpd", "vfmsubaddpd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubaddpd>, BX_ISA_FMA4, OP_Vpd, OP_Hpd, OP_VIb, OP_Wpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBADDPD_VpdHpdWpdVIb, "vfmsubaddpd", "vfmsubaddpd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubaddpd>, BX_ISA_FMA4, OP_Vpd, OP_Hpd, OP_Wpd, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDPS_VpsHpsVIbWps, "vfmaddps", "vfmaddps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddps>, BX_ISA_FMA4, OP_Vps, OP_Hps, OP_VIb, OP_Wps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDPS_VpsHpsWpsVIb, "vfmaddps", "vfmaddps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddps>, BX_ISA_FMA4, OP_Vps, OP_Hps, OP_Wps, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDPD_VpdHpdVIbWpd, "vfmaddpd", "vfmaddpd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddpd>, BX_ISA_FMA4, OP_Vpd, OP_Hpd, OP_VIb, OP_Wpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDPD_VpdHpdWpdVIb, "vfmaddpd", "vfmaddpd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddpd>, BX_ISA_FMA4, OP_Vpd, OP_Hpd, OP_Wpd, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDSS_VssHssVIbWss, "vfmaddss", "vfmaddss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMADDSS_VssHssWssVIbR, BX_ISA_FMA4, OP_Vss, OP_Hss, OP_VIb, OP_Wss, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDSS_VssHssWssVIb, "vfmaddss", "vfmaddss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMADDSS_VssHssWssVIbR, BX_ISA_FMA4, OP_Vss, OP_Hss, OP_Wss, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDSD_VsdHsdVIbWsd, "vfmaddsd", "vfmaddsd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMADDSD_VsdHsdWsdVIbR, BX_ISA_FMA4, OP_Vsd, OP_Hsd, OP_VIb, OP_Wsd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMADDSD_VsdHsdWsdVIb, "vfmaddsd", "vfmaddsd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMADDSD_VsdHsdWsdVIbR, BX_ISA_FMA4, OP_Vsd, OP_Hsd, OP_Wsd, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBPS_VpsHpsVIbWps, "vfmsubps", "vfmsubps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPS_VpsHpsWpsR, BX_ISA_FMA4, OP_Vps, OP_Hps, OP_VIb, OP_Wps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBPS_VpsHpsWpsVIb, "vfmsubps", "vfmsubps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPS_VpsHpsWpsR, BX_ISA_FMA4, OP_Vps, OP_Hps, OP_Wps, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBPD_VpdHpdVIbWpd, "vfmsubpd", "vfmsubpd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPD_VpdHpdWpdR, BX_ISA_FMA4, OP_Vpd, OP_Hpd, OP_VIb, OP_Wpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBPD_VpdHpdWpdVIb, "vfmsubpd", "vfmsubpd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMSUBPD_VpdHpdWpdR, BX_ISA_FMA4, OP_Vpd, OP_Hpd, OP_Wpd, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBPS_VpsHpsVIbWps, "vfmsubps", "vfmsubps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubps>, BX_ISA_FMA4, OP_Vps, OP_Hps, OP_VIb, OP_Wps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBPS_VpsHpsWpsVIb, "vfmsubps", "vfmsubps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubps>, BX_ISA_FMA4, OP_Vps, OP_Hps, OP_Wps, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBPD_VpdHpdVIbWpd, "vfmsubpd", "vfmsubpd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubpd>, BX_ISA_FMA4, OP_Vpd, OP_Hpd, OP_VIb, OP_Wpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBPD_VpdHpdWpdVIb, "vfmsubpd", "vfmsubpd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubpd>, BX_ISA_FMA4, OP_Vpd, OP_Hpd, OP_Wpd, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBSS_VssHssVIbWss, "vfmsubss", "vfmsubss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMSUBSS_VssHssWssVIbR, BX_ISA_FMA4, OP_Vss, OP_Hss, OP_VIb, OP_Wss, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBSS_VssHssWssVIb, "vfmsubss", "vfmsubss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMSUBSS_VssHssWssVIbR, BX_ISA_FMA4, OP_Vss, OP_Hss, OP_Wss, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBSD_VsdHsdVIbWsd, "vfmsubsd", "vfmsubsd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMSUBSD_VsdHsdWsdVIbR, BX_ISA_FMA4, OP_Vsd, OP_Hsd, OP_VIb, OP_Wsd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFMSUBSD_VsdHsdWsdVIb, "vfmsubsd", "vfmsubsd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMSUBSD_VsdHsdWsdVIbR, BX_ISA_FMA4, OP_Vsd, OP_Hsd, OP_Wsd, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMADDPS_VpsHpsVIbWps, "vfnmaddps", "vfnmaddps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPS_VpsHpsWpsR, BX_ISA_FMA4, OP_Vps, OP_Hps, OP_VIb, OP_Wps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMADDPS_VpsHpsWpsVIb, "vfnmaddps", "vfnmaddps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPS_VpsHpsWpsR, BX_ISA_FMA4, OP_Vps, OP_Hps, OP_Wps, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMADDPD_VpdHpdVIbWpd, "vfnmaddpd", "vfnmaddpd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPD_VpdHpdWpdR, BX_ISA_FMA4, OP_Vpd, OP_Hpd, OP_VIb, OP_Wpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMADDPD_VpdHpdWpdVIb, "vfnmaddpd", "vfnmaddpd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMADDPD_VpdHpdWpdR, BX_ISA_FMA4, OP_Vpd, OP_Hpd, OP_Wpd, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMADDPS_VpsHpsVIbWps, "vfnmaddps", "vfnmaddps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmaddps>, BX_ISA_FMA4, OP_Vps, OP_Hps, OP_VIb, OP_Wps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMADDPS_VpsHpsWpsVIb, "vfnmaddps", "vfnmaddps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmaddps>, BX_ISA_FMA4, OP_Vps, OP_Hps, OP_Wps, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMADDPD_VpdHpdVIbWpd, "vfnmaddpd", "vfnmaddpd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmaddpd>, BX_ISA_FMA4, OP_Vpd, OP_Hpd, OP_VIb, OP_Wpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMADDPD_VpdHpdWpdVIb, "vfnmaddpd", "vfnmaddpd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmaddpd>, BX_ISA_FMA4, OP_Vpd, OP_Hpd, OP_Wpd, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMADDSS_VssHssVIbWss, "vfnmaddss", "vfnmaddss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMADDSS_VssHssWssVIbR, BX_ISA_FMA4, OP_Vss, OP_Hss, OP_VIb, OP_Wss, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMADDSS_VssHssWssVIb, "vfnmaddss", "vfnmaddss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMADDSS_VssHssWssVIbR, BX_ISA_FMA4, OP_Vss, OP_Hss, OP_Wss, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMADDSD_VsdHsdVIbWsd, "vfnmaddsd", "vfnmaddsd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMADDSD_VsdHsdWsdVIbR, BX_ISA_FMA4, OP_Vsd, OP_Hsd, OP_VIb, OP_Wsd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMADDSD_VsdHsdWsdVIb, "vfnmaddsd", "vfnmaddsd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMADDSD_VsdHsdWsdVIbR, BX_ISA_FMA4, OP_Vsd, OP_Hsd, OP_Wsd, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMSUBPS_VpsHpsVIbWps, "vfnmsubps", "vfnmsubps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPS_VpsHpsWpsR, BX_ISA_FMA4, OP_Vps, OP_Hps, OP_VIb, OP_Wps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMSUBPS_VpsHpsWpsVIb, "vfnmsubps", "vfnmsubps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPS_VpsHpsWpsR, BX_ISA_FMA4, OP_Vps, OP_Hps, OP_Wps, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMSUBPD_VpdHpdVIbWpd, "vfnmsubpd", "vfnmsubpd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPD_VpdHpdWpdR, BX_ISA_FMA4, OP_Vpd, OP_Hpd, OP_VIb, OP_Wpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMSUBPD_VpdHpdWpdVIb, "vfnmsubpd", "vfnmsubpd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFNMSUBPD_VpdHpdWpdR, BX_ISA_FMA4, OP_Vpd, OP_Hpd, OP_Wpd, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMSUBPS_VpsHpsVIbWps, "vfnmsubps", "vfnmsubps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmsubps>, BX_ISA_FMA4, OP_Vps, OP_Hps, OP_VIb, OP_Wps, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMSUBPS_VpsHpsWpsVIb, "vfnmsubps", "vfnmsubps", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmsubps>, BX_ISA_FMA4, OP_Vps, OP_Hps, OP_Wps, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMSUBPD_VpdHpdVIbWpd, "vfnmsubpd", "vfnmsubpd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmsubpd>, BX_ISA_FMA4, OP_Vpd, OP_Hpd, OP_VIb, OP_Wpd, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMSUBPD_VpdHpdWpdVIb, "vfnmsubpd", "vfnmsubpd", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmsubpd>, BX_ISA_FMA4, OP_Vpd, OP_Hpd, OP_Wpd, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMSUBSS_VssHssVIbWss, "vfnmsubss", "vfnmsubss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMSUBSS_VssHssWssVIbR, BX_ISA_FMA4, OP_Vss, OP_Hss, OP_VIb, OP_Wss, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMSUBSS_VssHssWssVIb, "vfnmsubss", "vfnmsubss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMSUBSS_VssHssWssVIbR, BX_ISA_FMA4, OP_Vss, OP_Hss, OP_Wss, OP_VIb, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VFNMSUBSD_VsdHsdVIbWsd, "vfnmsubsd", "vfnmsubsd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMSUBSD_VsdHsdWsdVIbR, BX_ISA_FMA4, OP_Vsd, OP_Hsd, OP_VIb, OP_Wsd, BX_PREPARE_AVX)
@ -2844,8 +2844,8 @@ bx_define_opcode(BX_IA_V512_VADDPD_VpdHpdWpd, "vaddpd", "vaddpd", &BX_CPU_C::LOA
bx_define_opcode(BX_IA_V512_VADDSS_VssHpsWss, "vaddss", "vaddss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VADDSS_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VADDSD_VsdHpdWsd, "vaddsd", "vaddsd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VADDSD_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VADDPS_VpsHpsWps_Kmask, "vaddps", "vaddps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_SINGLE<xmm_addps_mask>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VADDPD_VpdHpdWpd_Kmask, "vaddpd", "vaddpd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_DOUBLE<xmm_addpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VADDPS_VpsHpsWps_Kmask, "vaddps", "vaddps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_2OP_SINGLE<xmm_addps_mask>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VADDPD_VpdHpdWpd_Kmask, "vaddpd", "vaddpd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_2OP_DOUBLE<xmm_addpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VADDSS_VssHpsWss_Kmask, "vaddss", "vaddss", &BX_CPU_C::LOAD_MASK_Wss, &BX_CPU_C::VADDSS_MASK_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VADDSD_VsdHpdWsd_Kmask, "vaddsd", "vaddsd", &BX_CPU_C::LOAD_MASK_Wsd, &BX_CPU_C::VADDSD_MASK_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
@ -2854,8 +2854,8 @@ bx_define_opcode(BX_IA_V512_VSUBPD_VpdHpdWpd, "vsubpd", "vsubpd", &BX_CPU_C::LOA
bx_define_opcode(BX_IA_V512_VSUBSS_VssHpsWss, "vsubss", "vsubss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VSUBSS_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VSUBSD_VsdHpdWsd, "vsubsd", "vsubsd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VSUBSD_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VSUBPS_VpsHpsWps_Kmask, "vsubps", "vsubps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_SINGLE<xmm_subps_mask>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VSUBPD_VpdHpdWpd_Kmask, "vsubpd", "vsubpd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_DOUBLE<xmm_subpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VSUBPS_VpsHpsWps_Kmask, "vsubps", "vsubps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_2OP_SINGLE<xmm_subps_mask>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VSUBPD_VpdHpdWpd_Kmask, "vsubpd", "vsubpd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_2OP_DOUBLE<xmm_subpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VSUBSS_VssHpsWss_Kmask, "vsubss", "vsubss", &BX_CPU_C::LOAD_MASK_Wss, &BX_CPU_C::VSUBSS_MASK_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VSUBSD_VsdHpdWsd_Kmask, "vsubsd", "vsubsd", &BX_CPU_C::LOAD_MASK_Wsd, &BX_CPU_C::VSUBSD_MASK_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
@ -2864,8 +2864,8 @@ bx_define_opcode(BX_IA_V512_VMULPD_VpdHpdWpd, "vmulpd", "vmulpd", &BX_CPU_C::LOA
bx_define_opcode(BX_IA_V512_VMULSS_VssHpsWss, "vmulss", "vmulss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMULSS_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VMULSD_VsdHpdWsd, "vmulsd", "vmulsd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMULSD_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VMULPS_VpsHpsWps_Kmask, "vmulps", "vmulps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_SINGLE<xmm_mulps_mask>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMULPD_VpdHpdWpd_Kmask, "vmulpd", "vmulpd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_DOUBLE<xmm_mulpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMULPS_VpsHpsWps_Kmask, "vmulps", "vmulps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_2OP_SINGLE<xmm_mulps_mask>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMULPD_VpdHpdWpd_Kmask, "vmulpd", "vmulpd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_2OP_DOUBLE<xmm_mulpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMULSS_VssHpsWss_Kmask, "vmulss", "vmulss", &BX_CPU_C::LOAD_MASK_Wss, &BX_CPU_C::VMULSS_MASK_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VMULSD_VsdHpdWsd_Kmask, "vmulsd", "vmulsd", &BX_CPU_C::LOAD_MASK_Wsd, &BX_CPU_C::VMULSD_MASK_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
@ -2874,8 +2874,8 @@ bx_define_opcode(BX_IA_V512_VDIVPD_VpdHpdWpd, "vdivpd", "vdivpd", &BX_CPU_C::LOA
bx_define_opcode(BX_IA_V512_VDIVSS_VssHpsWss, "vdivss", "vdivss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VDIVSS_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VDIVSD_VsdHpdWsd, "vdivsd", "vdivsd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VDIVSD_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VDIVPS_VpsHpsWps_Kmask, "vdivps", "vdivps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_SINGLE<xmm_divps_mask>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VDIVPD_VpdHpdWpd_Kmask, "vdivpd", "vdivpd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_DOUBLE<xmm_divpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VDIVPS_VpsHpsWps_Kmask, "vdivps", "vdivps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_2OP_SINGLE<xmm_divps_mask>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VDIVPD_VpdHpdWpd_Kmask, "vdivpd", "vdivpd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_2OP_DOUBLE<xmm_divpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VDIVSS_VssHpsWss_Kmask, "vdivss", "vdivss", &BX_CPU_C::LOAD_MASK_Wss, &BX_CPU_C::VDIVSS_MASK_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VDIVSD_VsdHpdWsd_Kmask, "vdivsd", "vdivsd", &BX_CPU_C::LOAD_MASK_Wsd, &BX_CPU_C::VDIVSD_MASK_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
@ -2884,8 +2884,8 @@ bx_define_opcode(BX_IA_V512_VMINPD_VpdHpdWpd, "vminpd", "vminpd", &BX_CPU_C::LOA
bx_define_opcode(BX_IA_V512_VMINSS_VssHpsWss, "vminss", "vminss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMINSS_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VMINSD_VsdHpdWsd, "vminsd", "vminsd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMINSD_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VMINPS_VpsHpsWps_Kmask, "vminps", "vminps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_SINGLE<xmm_minps_mask>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMINPD_VpdHpdWpd_Kmask, "vminpd", "vminpd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_DOUBLE<xmm_minpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMINPS_VpsHpsWps_Kmask, "vminps", "vminps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_2OP_SINGLE<xmm_minps_mask>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMINPD_VpdHpdWpd_Kmask, "vminpd", "vminpd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_2OP_DOUBLE<xmm_minpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMINSS_VssHpsWss_Kmask, "vminss", "vminss", &BX_CPU_C::LOAD_MASK_Wss, &BX_CPU_C::VMINSS_MASK_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VMINSD_VsdHpdWsd_Kmask, "vminsd", "vminsd", &BX_CPU_C::LOAD_MASK_Wsd, &BX_CPU_C::VMINSD_MASK_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
@ -2894,13 +2894,13 @@ bx_define_opcode(BX_IA_V512_VMAXPD_VpdHpdWpd, "vmaxpd", "vmaxpd", &BX_CPU_C::LOA
bx_define_opcode(BX_IA_V512_VMAXSS_VssHpsWss, "vmaxss", "vmaxss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMAXSS_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VMAXSD_VsdHpdWsd, "vmaxsd", "vmaxsd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMAXSD_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VMAXPS_VpsHpsWps_Kmask, "vmaxps", "vmaxps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_SINGLE<xmm_maxps_mask>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMAXPD_VpdHpdWpd_Kmask, "vmaxpd", "vmaxpd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_DOUBLE<xmm_maxpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMAXPS_VpsHpsWps_Kmask, "vmaxps", "vmaxps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_2OP_SINGLE<xmm_maxps_mask>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMAXPD_VpdHpdWpd_Kmask, "vmaxpd", "vmaxpd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_2OP_DOUBLE<xmm_maxpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMAXSS_VssHpsWss_Kmask, "vmaxss", "vmaxss", &BX_CPU_C::LOAD_MASK_Wss, &BX_CPU_C::VMAXSS_MASK_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VMAXSD_VsdHpdWsd_Kmask, "vmaxsd", "vmaxsd", &BX_CPU_C::LOAD_MASK_Wsd, &BX_CPU_C::VMAXSD_MASK_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VSQRTPS_VpsWps, "vsqrtps", "vsqrtps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VSQRTPS_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_mVps, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VSQRTPD_VpdWpd, "vsqrtpd", "vsqrtpd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VSQRTPD_VpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_mVpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VSQRTPS_VpsWps, "vsqrtps", "vsqrtps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::HANDLE_AVX_PFP_1OP<xmm_sqrtps>, BX_ISA_AVX512, OP_Vps, OP_mVps, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VSQRTPD_VpdWpd, "vsqrtpd", "vsqrtpd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::HANDLE_AVX_PFP_1OP<xmm_sqrtpd>, BX_ISA_AVX512, OP_Vpd, OP_mVpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VSQRTSS_VssHpsWss, "vsqrtss", "vsqrtss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VSQRTSS_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VSQRTSD_VsdHpdWsd, "vsqrtsd", "vsqrtsd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VSQRTSD_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
@ -3573,8 +3573,8 @@ bx_define_opcode(BX_IA_V512_VSCALEFPD_VpdHpdWpd, "vscalefpd", "vscalefpd", &BX_C
bx_define_opcode(BX_IA_V512_VSCALEFSS_VssHpsWss, "vscalefss", "vscalefss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VSCALEFSS_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VSCALEFSD_VsdHpdWsd, "vscalefsd", "vscalefsd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VSCALEFSD_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VSCALEFPS_VpsHpsWps_Kmask, "vscalefps", "vscalefps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_SINGLE<xmm_scalefps_mask>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VSCALEFPD_VpdHpdWpd_Kmask, "vscalefpd", "vscalefpd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_DOUBLE<xmm_scalefpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VSCALEFPS_VpsHpsWps_Kmask, "vscalefps", "vscalefps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_2OP_SINGLE<xmm_scalefps_mask>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VSCALEFPD_VpdHpdWpd_Kmask, "vscalefpd", "vscalefpd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_2OP_DOUBLE<xmm_scalefpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VSCALEFSS_VssHpsWss_Kmask, "vscalefss", "vscalefss", &BX_CPU_C::LOAD_MASK_Wss, &BX_CPU_C::VSCALEFSS_MASK_VssHpsWssR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_mVss, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VSCALEFSD_VsdHpdWsd_Kmask, "vscalefsd", "vscalefsd", &BX_CPU_C::LOAD_MASK_Wsd, &BX_CPU_C::VSCALEFSD_MASK_VsdHpdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_mVsd, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
@ -3638,19 +3638,19 @@ bx_define_opcode(BX_IA_V512_VCVTQQ2PS_VpsWdq, "vcvtqq2ps", "vcvtqq2ps", &BX_CPU_
bx_define_opcode(BX_IA_V512_VCVTDQ2PS_VpsWdq_Kmask, "vcvtdq2ps", "vcvtdq2ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VCVTDQ2PS_MASK_VpsWdqR, BX_ISA_AVX512, OP_Vps, OP_mVdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VCVTQQ2PS_VpsWdq_Kmask, "vcvtqq2ps", "vcvtqq2ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VCVTQQ2PS_MASK_VpsWdqR, BX_ISA_AVX512_DQ, OP_Vps, OP_mVdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADD132PS_VpsHpsWps, "vfmadd132ps", "vfmadd132ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADD132PD_VpdHpdWpd, "vfmadd132pd", "vfmadd132pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADD213PS_VpsHpsWps, "vfmadd213ps", "vfmadd213ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADD213PD_VpdHpdWpd, "vfmadd213pd", "vfmadd213pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADD231PS_VpsHpsWps, "vfmadd231ps", "vfmadd231ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADD231PD_VpdHpdWpd, "vfmadd231pd", "vfmadd231pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADD132PS_VpsHpsWps, "vfmadd132ps", "vfmadd132ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddps>, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADD132PD_VpdHpdWpd, "vfmadd132pd", "vfmadd132pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddpd>, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADD213PS_VpsHpsWps, "vfmadd213ps", "vfmadd213ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddps>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADD213PD_VpdHpdWpd, "vfmadd213pd", "vfmadd213pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddpd>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADD231PS_VpsHpsWps, "vfmadd231ps", "vfmadd231ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddps>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADD231PD_VpdHpdWpd, "vfmadd231pd", "vfmadd231pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddpd>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADD132PS_VpsHpsWps_Kmask, "vfmadd132ps", "vfmadd132ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMADDPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADD132PD_VpdHpdWpd_Kmask, "vfmadd132pd", "vfmadd132pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMADDPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADD213PS_VpsHpsWps_Kmask, "vfmadd213ps", "vfmadd213ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMADDPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADD213PD_VpdHpdWpd_Kmask, "vfmadd213pd", "vfmadd213pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMADDPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADD231PS_VpsHpsWps_Kmask, "vfmadd231ps", "vfmadd231ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMADDPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADD231PD_VpdHpdWpd_Kmask, "vfmadd231pd", "vfmadd231pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMADDPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADD132PS_VpsHpsWps_Kmask, "vfmadd132ps", "vfmadd132ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_SINGLE<xmm_fmaddps_mask>, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADD132PD_VpdHpdWpd_Kmask, "vfmadd132pd", "vfmadd132pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_DOUBLE<xmm_fmaddpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADD213PS_VpsHpsWps_Kmask, "vfmadd213ps", "vfmadd213ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_SINGLE<xmm_fmaddps_mask>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADD213PD_VpdHpdWpd_Kmask, "vfmadd213pd", "vfmadd213pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_DOUBLE<xmm_fmaddpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADD231PS_VpsHpsWps_Kmask, "vfmadd231ps", "vfmadd231ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_SINGLE<xmm_fmaddps_mask>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADD231PD_VpdHpdWpd_Kmask, "vfmadd231pd", "vfmadd231pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_DOUBLE<xmm_fmaddpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADD132SS_VpsHssWss, "vfmadd132ss", "vfmadd132ss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMADDSS_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Vss, OP_mVss, OP_Hss, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VFMADD132SD_VpdHsdWsd, "vfmadd132sd", "vfmadd132sd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMADDSD_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Vsd, OP_mVsd, OP_Hsd, BX_PREPARE_EVEX_NO_BROADCAST)
@ -3666,47 +3666,47 @@ bx_define_opcode(BX_IA_V512_VFMADD213SD_VpdHsdWsd_Kmask, "vfmadd213sd", "vfmadd2
bx_define_opcode(BX_IA_V512_VFMADD231SS_VpsHssWss_Kmask, "vfmadd231ss", "vfmadd231ss", &BX_CPU_C::LOAD_MASK_Wss, &BX_CPU_C::VFMADDSS_MASK_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_mVss, OP_Vss, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VFMADD231SD_VpdHsdWsd_Kmask, "vfmadd231sd", "vfmadd231sd", &BX_CPU_C::LOAD_MASK_Wsd, &BX_CPU_C::VFMADDSD_MASK_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_mVsd, OP_Vsd, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VFMADDSUB132PS_VpsHpsWps, "vfmaddsub132ps", "vfmaddsub132ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMADDSUBPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADDSUB132PD_VpdHpdWpd, "vfmaddsub132pd", "vfmaddsub132pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMADDSUBPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADDSUB213PS_VpsHpsWps, "vfmaddsub213ps", "vfmaddsub213ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMADDSUBPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADDSUB213PD_VpdHpdWpd, "vfmaddsub213pd", "vfmaddsub213pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMADDSUBPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADDSUB231PS_VpsHpsWps, "vfmaddsub231ps", "vfmaddsub231ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMADDSUBPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADDSUB231PD_VpdHpdWpd, "vfmaddsub231pd", "vfmaddsub231pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMADDSUBPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADDSUB132PS_VpsHpsWps, "vfmaddsub132ps", "vfmaddsub132ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddsubps>, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADDSUB132PD_VpdHpdWpd, "vfmaddsub132pd", "vfmaddsub132pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddsubpd>, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADDSUB213PS_VpsHpsWps, "vfmaddsub213ps", "vfmaddsub213ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddsubps>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADDSUB213PD_VpdHpdWpd, "vfmaddsub213pd", "vfmaddsub213pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddsubpd>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADDSUB231PS_VpsHpsWps, "vfmaddsub231ps", "vfmaddsub231ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddsubps>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADDSUB231PD_VpdHpdWpd, "vfmaddsub231pd", "vfmaddsub231pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmaddsubpd>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADDSUB132PS_VpsHpsWps_Kmask, "vfmaddsub132ps", "vfmaddsub132ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMADDSUBPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADDSUB132PD_VpdHpdWpd_Kmask, "vfmaddsub132pd", "vfmaddsub132pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMADDSUBPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADDSUB213PS_VpsHpsWps_Kmask, "vfmaddsub213ps", "vfmaddsub213ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMADDSUBPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADDSUB213PD_VpdHpdWpd_Kmask, "vfmaddsub213pd", "vfmaddsub213pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMADDSUBPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADDSUB231PS_VpsHpsWps_Kmask, "vfmaddsub231ps", "vfmaddsub231ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMADDSUBPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADDSUB231PD_VpdHpdWpd_Kmask, "vfmaddsub231pd", "vfmaddsub231pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMADDSUBPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADDSUB132PS_VpsHpsWps_Kmask, "vfmaddsub132ps", "vfmaddsub132ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_SINGLE<xmm_fmaddsubps_mask>, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADDSUB132PD_VpdHpdWpd_Kmask, "vfmaddsub132pd", "vfmaddsub132pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_DOUBLE<xmm_fmaddsubpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADDSUB213PS_VpsHpsWps_Kmask, "vfmaddsub213ps", "vfmaddsub213ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_SINGLE<xmm_fmaddsubps_mask>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADDSUB213PD_VpdHpdWpd_Kmask, "vfmaddsub213pd", "vfmaddsub213pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_DOUBLE<xmm_fmaddsubpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADDSUB231PS_VpsHpsWps_Kmask, "vfmaddsub231ps", "vfmaddsub231ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_SINGLE<xmm_fmaddsubps_mask>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADDSUB231PD_VpdHpdWpd_Kmask, "vfmaddsub231pd", "vfmaddsub231pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_DOUBLE<xmm_fmaddsubpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUBADD132PS_VpsHpsWps, "vfmsubadd132ps", "vfmsubadd132ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMSUBADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUBADD132PD_VpdHpdWpd, "vfmsubadd132pd", "vfmsubadd132pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMSUBADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUBADD213PS_VpsHpsWps, "vfmsubadd213ps", "vfmsubadd213ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMSUBADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUBADD213PD_VpdHpdWpd, "vfmsubadd213pd", "vfmsubadd213pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMSUBADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUBADD231PS_VpsHpsWps, "vfmsubadd231ps", "vfmsubadd231ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMSUBADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUBADD231PD_VpdHpdWpd, "vfmsubadd231pd", "vfmsubadd231pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMSUBADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUBADD132PS_VpsHpsWps, "vfmsubadd132ps", "vfmsubadd132ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubaddps>, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUBADD132PD_VpdHpdWpd, "vfmsubadd132pd", "vfmsubadd132pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubaddpd>, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUBADD213PS_VpsHpsWps, "vfmsubadd213ps", "vfmsubadd213ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubaddps>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUBADD213PD_VpdHpdWpd, "vfmsubadd213pd", "vfmsubadd213pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubaddpd>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUBADD231PS_VpsHpsWps, "vfmsubadd231ps", "vfmsubadd231ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubaddps>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUBADD231PD_VpdHpdWpd, "vfmsubadd231pd", "vfmsubadd231pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubaddpd>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUBADD132PS_VpsHpsWps_Kmask, "vfmsubadd132ps", "vfmsubadd132ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMSUBADDPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUBADD132PD_VpdHpdWpd_Kmask, "vfmsubadd132pd", "vfmsubadd132pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMSUBADDPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUBADD213PS_VpsHpsWps_Kmask, "vfmsubadd213ps", "vfmsubadd213ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMSUBADDPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUBADD213PD_VpdHpdWpd_Kmask, "vfmsubadd213pd", "vfmsubadd213pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMSUBADDPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUBADD231PS_VpsHpsWps_Kmask, "vfmsubadd231ps", "vfmsubadd231ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMSUBADDPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUBADD231PD_VpdHpdWpd_Kmask, "vfmsubadd231pd", "vfmsubadd231pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMSUBADDPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUBADD132PS_VpsHpsWps_Kmask, "vfmsubadd132ps", "vfmsubadd132ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_SINGLE<xmm_fmsubaddps_mask>, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUBADD132PD_VpdHpdWpd_Kmask, "vfmsubadd132pd", "vfmsubadd132pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_DOUBLE<xmm_fmsubaddpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUBADD213PS_VpsHpsWps_Kmask, "vfmsubadd213ps", "vfmsubadd213ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_SINGLE<xmm_fmsubaddps_mask>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUBADD213PD_VpdHpdWpd_Kmask, "vfmsubadd213pd", "vfmsubadd213pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_DOUBLE<xmm_fmsubaddpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUBADD231PS_VpsHpsWps_Kmask, "vfmsubadd231ps", "vfmsubadd231ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_SINGLE<xmm_fmsubaddps_mask>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUBADD231PD_VpdHpdWpd_Kmask, "vfmsubadd231pd", "vfmsubadd231pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_DOUBLE<xmm_fmsubaddpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUB132PS_VpsHpsWps, "vfmsub132ps", "vfmsub132ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMSUBPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUB132PD_VpdHpdWpd, "vfmsub132pd", "vfmsub132pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMSUBPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUB213PS_VpsHpsWps, "vfmsub213ps", "vfmsub213ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMSUBPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUB213PD_VpdHpdWpd, "vfmsub213pd", "vfmsub213pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMSUBPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUB231PS_VpsHpsWps, "vfmsub231ps", "vfmsub231ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMSUBPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUB231PD_VpdHpdWpd, "vfmsub231pd", "vfmsub231pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMSUBPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUB132PS_VpsHpsWps, "vfmsub132ps", "vfmsub132ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubps>, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUB132PD_VpdHpdWpd, "vfmsub132pd", "vfmsub132pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubpd>, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUB213PS_VpsHpsWps, "vfmsub213ps", "vfmsub213ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubps>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUB213PD_VpdHpdWpd, "vfmsub213pd", "vfmsub213pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubpd>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUB231PS_VpsHpsWps, "vfmsub231ps", "vfmsub231ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubps>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUB231PD_VpdHpdWpd, "vfmsub231pd", "vfmsub231pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fmsubpd>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUB132PS_VpsHpsWps_Kmask, "vfmsub132ps", "vfmsub132ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMSUBPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUB132PD_VpdHpdWpd_Kmask, "vfmsub132pd", "vfmsub132pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMSUBPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUB213PS_VpsHpsWps_Kmask, "vfmsub213ps", "vfmsub213ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMSUBPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUB213PD_VpdHpdWpd_Kmask, "vfmsub213pd", "vfmsub213pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMSUBPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUB231PS_VpsHpsWps_Kmask, "vfmsub231ps", "vfmsub231ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFMSUBPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUB231PD_VpdHpdWpd_Kmask, "vfmsub231pd", "vfmsub231pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFMSUBPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUB132PS_VpsHpsWps_Kmask, "vfmsub132ps", "vfmsub132ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_SINGLE<xmm_fmsubps_mask>, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUB132PD_VpdHpdWpd_Kmask, "vfmsub132pd", "vfmsub132pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_DOUBLE<xmm_fmsubpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUB213PS_VpsHpsWps_Kmask, "vfmsub213ps", "vfmsub213ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_SINGLE<xmm_fmsubps_mask>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUB213PD_VpdHpdWpd_Kmask, "vfmsub213pd", "vfmsub213pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_DOUBLE<xmm_fmsubpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUB231PS_VpsHpsWps_Kmask, "vfmsub231ps", "vfmsub231ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_SINGLE<xmm_fmsubps_mask>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUB231PD_VpdHpdWpd_Kmask, "vfmsub231pd", "vfmsub231pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_DOUBLE<xmm_fmsubpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMSUB132SS_VpsHssWss, "vfmsub132ss", "vfmsub132ss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFMSUBSS_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Vss, OP_mVss, OP_Hss, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VFMSUB132SD_VpdHsdWsd, "vfmsub132sd", "vfmsub132sd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFMSUBSD_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Vsd, OP_mVsd, OP_Hsd, BX_PREPARE_EVEX_NO_BROADCAST)
@ -3722,19 +3722,19 @@ bx_define_opcode(BX_IA_V512_VFMSUB213SD_VpdHsdWsd_Kmask, "vfmsub213sd", "vfmsub2
bx_define_opcode(BX_IA_V512_VFMSUB231SS_VpsHssWss_Kmask, "vfmsub231ss", "vfmsub231ss", &BX_CPU_C::LOAD_MASK_Wss, &BX_CPU_C::VFMSUBSS_MASK_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_mVss, OP_Vss, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VFMSUB231SD_VpdHsdWsd_Kmask, "vfmsub231sd", "vfmsub231sd", &BX_CPU_C::LOAD_MASK_Wsd, &BX_CPU_C::VFMSUBSD_MASK_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_mVsd, OP_Vsd, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VFNMADD132PS_VpsHpsWps, "vfnmadd132ps", "vfnmadd132ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFNMADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMADD132PD_VpdHpdWpd, "vfnmadd132pd", "vfnmadd132pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFNMADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMADD213PS_VpsHpsWps, "vfnmadd213ps", "vfnmadd213ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFNMADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMADD213PD_VpdHpdWpd, "vfnmadd213pd", "vfnmadd213pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFNMADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMADD231PS_VpsHpsWps, "vfnmadd231ps", "vfnmadd231ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFNMADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMADD231PD_VpdHpdWpd, "vfnmadd231pd", "vfnmadd231pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFNMADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMADD132PS_VpsHpsWps, "vfnmadd132ps", "vfnmadd132ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmaddps>, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMADD132PD_VpdHpdWpd, "vfnmadd132pd", "vfnmadd132pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmaddpd>, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMADD213PS_VpsHpsWps, "vfnmadd213ps", "vfnmadd213ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmaddps>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMADD213PD_VpdHpdWpd, "vfnmadd213pd", "vfnmadd213pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmaddpd>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMADD231PS_VpsHpsWps, "vfnmadd231ps", "vfnmadd231ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmaddps>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMADD231PD_VpdHpdWpd, "vfnmadd231pd", "vfnmadd231pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmaddpd>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMADD132PS_VpsHpsWps_Kmask, "vfnmadd132ps", "vfnmadd132ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFNMADDPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMADD132PD_VpdHpdWpd_Kmask, "vfnmadd132pd", "vfnmadd132pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFNMADDPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMADD213PS_VpsHpsWps_Kmask, "vfnmadd213ps", "vfnmadd213ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFNMADDPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMADD213PD_VpdHpdWpd_Kmask, "vfnmadd213pd", "vfnmadd213pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFNMADDPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMADD231PS_VpsHpsWps_Kmask, "vfnmadd231ps", "vfnmadd231ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFNMADDPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMADD231PD_VpdHpdWpd_Kmask, "vfnmadd231pd", "vfnmadd231pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFNMADDPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMADD132PS_VpsHpsWps_Kmask, "vfnmadd132ps", "vfnmadd132ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_SINGLE<xmm_fnmaddps_mask>, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMADD132PD_VpdHpdWpd_Kmask, "vfnmadd132pd", "vfnmadd132pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_DOUBLE<xmm_fnmaddpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMADD213PS_VpsHpsWps_Kmask, "vfnmadd213ps", "vfnmadd213ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_SINGLE<xmm_fnmaddps_mask>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMADD213PD_VpdHpdWpd_Kmask, "vfnmadd213pd", "vfnmadd213pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_DOUBLE<xmm_fnmaddpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMADD231PS_VpsHpsWps_Kmask, "vfnmadd231ps", "vfnmadd231ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_SINGLE<xmm_fnmaddps_mask>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMADD231PD_VpdHpdWpd_Kmask, "vfnmadd231pd", "vfnmadd231pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_DOUBLE<xmm_fnmaddpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMADD132SS_VpsHssWss, "vfnmadd132ss", "vfnmadd132ss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMADDSS_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Vss, OP_mVss, OP_Hss, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VFNMADD132SD_VpdHsdWsd, "vfnmadd132sd", "vfnmadd132sd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMADDSD_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Vsd, OP_mVsd, OP_Hsd, BX_PREPARE_EVEX_NO_BROADCAST)
@ -3750,19 +3750,19 @@ bx_define_opcode(BX_IA_V512_VFNMADD213SD_VpdHsdWsd_Kmask, "vfnmadd213sd", "vfnma
bx_define_opcode(BX_IA_V512_VFNMADD231SS_VpsHssWss_Kmask, "vfnmadd231ss", "vfnmadd231ss", &BX_CPU_C::LOAD_MASK_Wss, &BX_CPU_C::VFNMADDSS_MASK_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Hss, OP_mVss, OP_Vss, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VFNMADD231SD_VpdHsdWsd_Kmask, "vfnmadd231sd", "vfnmadd231sd", &BX_CPU_C::LOAD_MASK_Wsd, &BX_CPU_C::VFNMADDSD_MASK_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Hsd, OP_mVsd, OP_Vsd, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VFNMSUB132PS_VpsHpsWps, "vfnmsub132ps", "vfnmsub132ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFNMSUBPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMSUB132PD_VpdHpdWpd, "vfnmsub132pd", "vfnmsub132pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFNMSUBPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMSUB213PS_VpsHpsWps, "vfnmsub213ps", "vfnmsub213ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFNMSUBPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMSUB213PD_VpdHpdWpd, "vfnmsub213pd", "vfnmsub213pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFNMSUBPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMSUB231PS_VpsHpsWps, "vfnmsub231ps", "vfnmsub231ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFNMSUBPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMSUB231PD_VpdHpdWpd, "vfnmsub231pd", "vfnmsub231pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFNMSUBPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMSUB132PS_VpsHpsWps, "vfnmsub132ps", "vfnmsub132ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmsubps>, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMSUB132PD_VpdHpdWpd, "vfnmsub132pd", "vfnmsub132pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmsubpd>, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMSUB213PS_VpsHpsWps, "vfnmsub213ps", "vfnmsub213ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmsubps>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMSUB213PD_VpdHpdWpd, "vfnmsub213pd", "vfnmsub213pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmsubpd>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMSUB231PS_VpsHpsWps, "vfnmsub231ps", "vfnmsub231ps", &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmsubps>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMSUB231PD_VpdHpdWpd, "vfnmsub231pd", "vfnmsub231pd", &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::HANDLE_AVX_PFP_3OP<xmm_fnmsubpd>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMSUB132PS_VpsHpsWps_Kmask, "vfnmsub132ps", "vfnmsub132ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFNMSUBPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMSUB132PD_VpdHpdWpd_Kmask, "vfnmsub132pd", "vfnmsub132pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFNMSUBPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMSUB213PS_VpsHpsWps_Kmask, "vfnmsub213ps", "vfnmsub213ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFNMSUBPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMSUB213PD_VpdHpdWpd_Kmask, "vfnmsub213pd", "vfnmsub213pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFNMSUBPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMSUB231PS_VpsHpsWps_Kmask, "vfnmsub231ps", "vfnmsub231ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::VFNMSUBPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMSUB231PD_VpdHpdWpd_Kmask, "vfnmsub231pd", "vfnmsub231pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VFNMSUBPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMSUB132PS_VpsHpsWps_Kmask, "vfnmsub132ps", "vfnmsub132ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_SINGLE<xmm_fnmsubps_mask>, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_mVps, OP_Hps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMSUB132PD_VpdHpdWpd_Kmask, "vfnmsub132pd", "vfnmsub132pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_DOUBLE<xmm_fnmsubpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_mVpd, OP_Hpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMSUB213PS_VpsHpsWps_Kmask, "vfnmsub213ps", "vfnmsub213ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_SINGLE<xmm_fnmsubps_mask>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_mVps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMSUB213PD_VpdHpdWpd_Kmask, "vfnmsub213pd", "vfnmsub213pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_DOUBLE<xmm_fnmsubpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Vpd, OP_mVpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMSUB231PS_VpsHpsWps_Kmask, "vfnmsub231ps", "vfnmsub231ps", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorD, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_SINGLE<xmm_fnmsubps_mask>, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVps, OP_Vps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMSUB231PD_VpdHpdWpd_Kmask, "vfnmsub231pd", "vfnmsub231pd", &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::HANDLE_AVX512_MASK_PFP_3OP_DOUBLE<xmm_fnmsubpd_mask>, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVpd, OP_Vpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFNMSUB132SS_VpsHssWss, "vfnmsub132ss", "vfnmsub132ss", &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VFNMSUBSS_VpsHssWssR, BX_ISA_AVX512, OP_Vps, OP_Vss, OP_mVss, OP_Hss, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VFNMSUB132SD_VpdHsdWsd, "vfnmsub132sd", "vfnmsub132sd", &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VFNMSUBSD_VpdHsdWsdR, BX_ISA_AVX512, OP_Vpd, OP_Vsd, OP_mVsd, OP_Hsd, BX_PREPARE_EVEX_NO_BROADCAST)

36
bochs/cpu/sse_pfp.cc
View File

@ -873,42 +873,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::COMISD_VsdWsdR(bxInstruction_c *i)
BX_NEXT_INSTR(i);
}
/*
* Opcode: 0F 51
* Square Root packed single precision.
* Possible floating point exceptions: #I, #D, #P
*/
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SQRTPS_VpsWpsR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
float_status_t status = mxcsr_to_softfloat_status_word(MXCSR);
xmm_sqrtps(&op, status);
check_exceptionsSSE(get_exception_flags(status));
BX_WRITE_XMM_REG(i->dst(), op);
#endif
BX_NEXT_INSTR(i);
}
/*
* Opcode: 66 0F 51
* Square Root packed double precision.
* Possible floating point exceptions: #I, #D, #P
*/
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SQRTPD_VpdWpdR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
float_status_t status = mxcsr_to_softfloat_status_word(MXCSR);
xmm_sqrtpd(&op, status);
check_exceptionsSSE(get_exception_flags(status));
BX_WRITE_XMM_REG(i->dst(), op);
#endif
BX_NEXT_INSTR(i);
}
/*
* Opcode: F2 0F 51
* Square Root scalar double precision.