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32 Commits

Author SHA1 Message Date
Stanislav Shwartsman
4b03966176 Implemented VDBPSADBW AVX512BW instruction 
The only missing AVX512BW/AVX512DQ opcodes are now:

"NDS.512.66.0F3A.W0 56 VREDUCEPS
 NDS.512.66.0F3A.W1 56 VREDUCEPD"
"NDS.512.66.0F3A.W0 57 VREDUCESS
 NDS.512.66.0F3A.W1 57 VREDUCESD"
 2014-08-05 20:18:42 +00:00
Stanislav Shwartsman
4455d9100b simplify code a little more 2014-08-05 19:20:15 +00:00
Stanislav Shwartsman
5b0d0519d5 fixed typo in prev checkin 2014-08-05 19:03:17 +00:00
Stanislav Shwartsman
2231ffb242 simplify legacy (sse and avx) sad calculation in simd_int.h 2014-08-05 19:01:01 +00:00
Stanislav Shwartsman
d8d4d2f0c1 Implemented VPSRLVW/VPSRAVW/VPSLLVW AVX512BW instructions 
The only missing AVX512BW/AVX512DQ opcodes are now:

"512.66.0F3A.W1 0F VPALIGNR"
"NDS.66.0F3A.W0 42 VDBPSADBW"

"NDS.512.66.0F3A.W0 50 VRANGEPS
 NDS.512.66.0F3A.W1 50 VRANGEPD"
"NDS.512.66.0F3A.W0 51 VRANGESS
 NDS.512.66.0F3A.W1 51 VRANGESD"

"NDS.512.66.0F3A.W0 56 VREDUCEPS
 NDS.512.66.0F3A.W1 56 VREDUCEPD"
"NDS.512.66.0F3A.W0 57 VREDUCESS
 NDS.512.66.0F3A.W1 57 VREDUCESD"
 2014-07-25 21:15:48 +00:00
Stanislav Shwartsman
9cc7b67369 bugfix 2014-07-22 20:49:58 +00:00
Stanislav Shwartsman
c4c8652a3b Implemented VPMOV?2? and VPMIN* AVX512 instructions 
The only missing AVX512BW/AVX512DQ opcodes are now:

"512.66.0F38.W1 10 VPSRLVW"
"512.66.0F38.W1 11 VPSRAVW"
"512.66.0F38.W1 12 VPSLLVW"

"512.66.0F3A.W1 0F VPALIGNR"
"NDS.66.0F3A.W0 42 VDBPSADBW"

"NDS.512.66.0F3A.W0 50 VRANGEPS
 NDS.512.66.0F3A.W1 50 VRANGEPD"
"NDS.512.66.0F3A.W0 51 VRANGESS
 NDS.512.66.0F3A.W1 51 VRANGESD"

"NDS.512.66.0F3A.W0 56 VREDUCEPS
 NDS.512.66.0F3A.W1 56 VREDUCEPD"
"NDS.512.66.0F3A.W0 57 VREDUCESS
 NDS.512.66.0F3A.W1 57 VREDUCESD"
 2014-07-22 20:36:55 +00:00
Stanislav Shwartsman
ad7ef68876 Implemented VMULLQ AVX512DQ instruction 
The only missing AVX512BW/AVX512DQ opcodes are now:

"512.66.0F38.W1 10 VPSRLVW"
"512.66.0F38.W1 11 VPSRAVW"
"512.66.0F38.W1 12 VPSLLVW"

"512.F3.0F38.W0 28 VPMOVM2B
 512.F3.0F38.W1 28 VPMOVM2W"
"512.F3.0F38.W0 29 VPMOVB2M
 512.F3.0F38.W1 29 VPMOVW2M"

"512.F3.0F38.W0 38 VPMOVM2D
 512.F3.0F38.W1 38 VPMOVM2Q"
"512.F3.0F38.W0 39 VPMOVD2M
 512.F3.0F38.W1 39 VPMOVQ2M"

"NDS.512.66.0F38.WIG 38 VPMINSB"
"NDS.512.66.0F38.WIG 3A VPMINUW"

"512.66.0F3A.W1 0F VPALIGNR"
"NDS.66.0F3A.W0 42 VDBPSADBW"

"NDS.512.66.0F3A.W0 50 VRANGEPS
 NDS.512.66.0F3A.W1 50 VRANGEPD"
"NDS.512.66.0F3A.W0 51 VRANGESS
 NDS.512.66.0F3A.W1 51 VRANGESD"

"NDS.512.66.0F3A.W0 56 VREDUCEPS
 NDS.512.66.0F3A.W1 56 VREDUCEPD"
"NDS.512.66.0F3A.W0 57 VREDUCESS
 NDS.512.66.0F3A.W1 57 VREDUCESD"
 2014-07-21 19:08:44 +00:00
Stanislav Shwartsman
94864fb9bc Implement AVX512BW and AVX512DQ extensions published in recently published Intel Archtecture Extensions manual rev20. 
https://software.intel.com/sites/default/files/managed/c6/a9/319433-020.pdf

Most of the instructions are implemented, more on the way.

+ few bugfixes for legacy AVX-512 emulation

AVX-512: Fixed bug in VCMPPS masked instruction implementation with 512-bit data size
AVX-512: Fixed AVX-512 masked convert instructions with non-k0 mask (behaved as non masked versions)
AVX-512: Fixed missed #UD due to invalid EVEX prefix fields for several AVX-512 opcodes (VFIXUPIMMSS/SD, FMA)
 2014-07-18 11:14:25 +00:00
Stanislav Shwartsman
402b2c01c9 Implemented AVX-512 conflict detection instructions (VPCONFLICT, VPLZCNT, VPBROADCASTMB2Q, VPBROADCASTMW2D) 
Only missed AVX-512 opcodes are:

512.66.0F38.W0 2C VSCALEFPS
512.66.0F38.W1 2C VSCALEFPD
NDS.LIG.66.0F38.W0 2D VSCALESS
NDS.LIG.66.0F38.W1 2D VSCALESD
 2014-02-27 21:12:02 +00:00
Stanislav Shwartsman
79c11cacbe fixed compilation err without avx 2014-01-23 17:08:30 +00:00
Stanislav Shwartsman
33889cd02e implemented avx-512 vpermq opcode 2014-01-22 21:21:32 +00:00
Stanislav Shwartsman
72c710947c code cleanups 2014-01-12 09:31:22 +00:00
Stanislav Shwartsman
ada455c4b9 just coding style 2013-12-22 20:48:26 +00:00
Stanislav Shwartsman
543b6c8254 compilation fix 2013-12-21 21:08:35 +00:00
Stanislav Shwartsman
979e10b725 added simd_int.h functions for future use 2013-12-21 20:46:27 +00:00
Stanislav Shwartsman
6d9b16e0f7 Implemented VCMPPS/PD/SS/SD AVX512 instructions 
Implemented AVX512 shift/rotate instructions
 2013-12-03 15:44:23 +00:00
Stanislav Shwartsman
0683b00535 implemented more avx-512 opcodes 2013-12-02 19:16:48 +00:00
Stanislav Shwartsman
79456eb7e1 Implemented VPCMP* AVX512 instructions 
Implemented VMOVNTPS/PD/DQ AVX512 instructions
Implemented VMOVNTDQA AVX512 instruction
Bugfixes for AVX-512
 2013-12-02 18:05:18 +00:00
Stanislav Shwartsman
c7b03eb00b implement avx-512 vpabsd/q instructions 2013-12-01 20:10:39 +00:00
Stanislav Shwartsman
21bb1363ac avx512 move functions introduced 2013-11-29 11:10:34 +00:00
Stanislav Shwartsman
d6d1c707df implemented set of integer avx512 instructions 2013-10-08 19:44:52 +00:00
Stanislav Shwartsman
3803ac7fbe fixed evex override mscsr controls 2013-09-19 21:38:25 +00:00
Stanislav Shwartsman
d169860f6c added masked operations to simd_pfp.h, optimize simd_int.h, rewrite dpps instr using new masked op from simd_pfp.h 2013-09-17 20:49:26 +00:00
Stanislav Shwartsman
aa25c1db6a name convention change - search and replace 2013-09-17 17:34:20 +00:00
Stanislav Shwartsman
1cebe5f83d rellback part of commit with xmm register access interface changes - doesn't work for big endian hosts 2013-09-16 19:10:42 +00:00
Stanislav Shwartsman
0cb0acc30f added evex decode tables - next step to populate them :) 2013-09-15 20:48:39 +00:00
Stanislav Shwartsman
574b69c81e fixed MSDEV warnings 2012-11-27 15:40:45 +00:00
Stanislav Shwartsman
b1a6b34616 implemented PERMIL2PS/PERMIL2PD XOP instructions 2011-10-20 17:37:57 +00:00
Stanislav Shwartsman
5cc04b9955 Implemented AMDs Buldozer XOP and TBM extensions. 
XOP: few instructions are still missing, coming soon

  BX_PANIC(("VPERMILPS_VpsHpsWpsVIbR: not implemented yet"));
  BX_PANIC(("VPERMILPD_VpdHpdWpdVIbR: not implemented yet"));
  BX_PANIC(("VPMADCSSWD_VdqHdqWdqVIbR: not implemented yet"));
  BX_PANIC(("VPMADCSWD_VdqHdqWdqVIbR: not implemented yet"));
  BX_PANIC(("VFRCZPS_VpsWpsR: not implemented yet"));
  BX_PANIC(("VFRCZPD_VpdWpdR: not implemented yet"));
  BX_PANIC(("VFRCZSS_VssWssR: not implemented yet"));
  BX_PANIC(("VFRCZSD_VsdWsdR: not implemented yet"));
 2011-10-19 20:54:04 +00:00
Stanislav Shwartsman
6bdfbeeffa fixed for gather VSIB calculation 2011-08-28 20:14:53 +00:00
Stanislav Shwartsman
44241a1e56 - Added support for AVX and AVX2 instructions emulation, to enable configure 
with --enable-avx option. When compiled in, AVX still has to be enabled
    using .bochsrc CPUID option. AVX2 FMA instructions still not implemented.

  - Added support for Bit Manipulation Instructions (BMI) emulation. The BMI
    instructions support can be enabled using .bochsrc CPUID option.
 2011-08-27 13:47:16 +00:00