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2767 Commits

Author SHA1 Message Date
Stanislav Shwartsman
f69bc016d2 vmx: nmi blocking after NMI event injection. better dbg print for VMEXIT 2012-10-04 16:15:58 +00:00
Stanislav Shwartsman
be1642e02e fixed compile with debugger enabled 2012-10-03 20:32:02 +00:00
Stanislav Shwartsman
2ca0c6c677 Move INTR, Local APIC INTR and SVN VINTR into new event interface (hardest part) 
Minor speedup (of 1-2%) was observed due to new implementation
Remove obsolete dbg_take_irq function and dbg_force_interrupt function from CPU code, the functions were not working properly anyway
 2012-10-03 20:24:29 +00:00
Stanislav Shwartsman
49bb3ba8f5 some cleanups and optimizations with new event interface 2012-10-03 15:49:45 +00:00
Stanislav Shwartsman
ae06a0825b svm virq - move to new event interface 2012-10-02 20:49:16 +00:00
Stanislav Shwartsman
9132c29280 optimization and code duplication cleanup in event handling code 2012-10-02 20:07:26 +00:00
Stanislav Shwartsman
dbb23aed43 close another SMC hole 2012-10-01 18:19:09 +00:00
Stanislav Shwartsman
3a6f649b18 fixed comment 2012-10-01 12:08:23 +00:00
Stanislav Shwartsman
e397a86ce0 fixed code duplication related to EXT field 2012-09-29 09:31:34 +00:00
Stanislav Shwartsman
dc369d831f small cleanup 2012-09-27 07:03:25 +00:00
Stanislav Shwartsman
8189a5ed20 fixed compilation with SMP 2012-09-26 16:00:49 +00:00
Stanislav Shwartsman
b2afa834c5 fixed compilation with intrumentation w/o x86-64 2012-09-25 20:48:46 +00:00
Stanislav Shwartsman
66a9a769fc fixed nmi window exiting 2012-09-25 20:00:33 +00:00
Stanislav Shwartsman
08d0ef6dbf fixes for new event handling code 2012-09-25 13:53:26 +00:00
Stanislav Shwartsman
d5f858d100 transfer VMX NMI window exiting into event vector infrastructure 2012-09-25 10:21:29 +00:00
Stanislav Shwartsman
40ba9c8d7b introducing new interface for handling CPU events based on vector of events and not on many not related variables. this is very initial implementation which takes into new interface only few events, more will code soon 2012-09-25 09:35:38 +00:00
Stanislav Shwartsman
f0c153e550 fixed warning 2012-09-24 19:53:49 +00:00
Stanislav Shwartsman
da150bc163 small optimization in icache 2012-09-23 19:35:46 +00:00
Stanislav Shwartsman
eb348992c2 optimize POPCNT implementation 2012-09-21 14:56:56 +00:00
Stanislav Shwartsman
74f5bb1934 WBINVD not necessary havw to flush ICACHE 2012-09-21 08:55:10 +00:00
Stanislav Shwartsman
f419798ca5 fixed reset value for mtrr 2012-09-15 19:52:11 +00:00
Stanislav Shwartsman
4f6557697b small comments updates in vmx code 2012-09-13 05:33:05 +00:00
Volker Ruppert
c2560a8d44 - fpu directory is now a subdirectory in 'cpu' 2012-09-12 21:08:40 +00:00
Stanislav Shwartsman
2c5165bc06 fix check of error_code feild on event injection 2012-09-12 04:12:58 +00:00
Stanislav Shwartsman
2f3c7ff8e4 implemented SMAP (Supervisor Mode Access Protection) from [Intel Architecture Instruction Set Extensions Programming Reference] rev14 
fixed enabling of ADX extensions in generic CPUID when enabled through .bochsrc

Small code cleanups on the way to implementation of APIC Registers Virtualization features disclosed in recent Intel SDM rev043
 2012-09-10 15:22:26 +00:00
Stanislav Shwartsman
0386f49e03 fixed comments for SHLD/SHRD instructrions and make code a little more clear 2012-09-09 17:44:42 +00:00
Stanislav Shwartsman
7e48b30b5d fixed random freeze issues caused by commit rev11402 2012-09-06 19:51:33 +00:00
Stanislav Shwartsman
bff3ba1535 small optimization in lazy flags code 2012-09-06 19:49:14 +00:00
Stanislav Shwartsman
f1fd44b2cf preparations for apic regs virtualization feature described in SDM rev044 2012-09-06 15:21:08 +00:00
Stanislav Shwartsman
8044a2bda6 rename i->execute field in the instruction 
move victim cache lookup into cache lookup so traces could be linked with victim cache hits directly
 2012-09-04 15:45:05 +00:00
Stanislav Shwartsman
295e3ab8db fixed compilation warning 2012-09-02 18:38:04 +00:00
Stanislav Shwartsman
d1879b839e increase icache size 2012-09-01 19:13:01 +00:00
Stanislav Shwartsman
86a06ff9f6 more new vmx defines 2012-08-31 15:38:28 +00:00
Stanislav Shwartsman
2a459fb9be add more disclosed VMCS fields and vmexit codes to enums (from rev44 published today) 2012-08-31 09:25:13 +00:00
Stanislav Shwartsman
40a9992aa6 small cleanups 2012-08-28 16:05:39 +00:00
Stanislav Shwartsman
e17cffab57 simplify generated code 2012-08-26 15:49:30 +00:00
Stanislav Shwartsman
c41cbe6d56 Link traces over taken branch optimization which makes handlers chaining even more efficient. 
I observed 5% speedup in all disk images over 2.6pre1.
The change is safe (passed all regressions) and I will be glad to make it into Bochs 2.6!
 2012-08-21 19:58:41 +00:00
Stanislav Shwartsman
399168e37d small cleanup 2012-08-19 18:44:08 +00:00
Stanislav Shwartsman
dd7b968404 SSE cvt instructions: transition from FPU to MMX state has higher priority than SSE exception (#XF/#UD) 2012-08-11 07:41:13 +00:00
Stanislav Shwartsman
df90b80352 set of small cpu fixes 2012-08-09 13:11:25 +00:00
Stanislav Shwartsman
0c11901d6b fixed segment limit check for AVX mem access - same fix for stores 2012-08-08 20:43:07 +00:00
Stanislav Shwartsman
af9e072ad6 fixed segment limit check for AVX mem access 2012-08-08 20:39:36 +00:00
Stanislav Shwartsman
be76f38b46 correct MOVBE decoding with prefix 0x66, also correct ADX decoding 2012-08-08 20:11:27 +00:00
Stanislav Shwartsman
fee1000ba2 split PINSRB instruction to /r and /m form 2012-08-07 14:38:43 +00:00
Stanislav Shwartsman
cac261553d Fixed stupid typo which caused incorrect VMX instr info on LDTR/TR instruction VMEXIT 2012-08-06 20:41:16 +00:00
Stanislav Shwartsman
cc694377b9 Standartization of Bochs instruction handlers. 
Bochs instruction emulation handlers won't refer to direct fields of instructions like MODRM.NNN or MODRM.RM anymore.
Use generic source/destination indications like SRC1, SRC2 and DST.
All handlers are modified to support new notation. In addition fetchDecode module was modified to assign sources to instructions properly.

Immediate benefits:
- Removal of several duplicated handlers (FMA3 duplicated with FMA4 is a trivial example)
- Simpler to understand fetch-decode code

Future benefits:
- Integration of disassembler into Bochs CPU module, ability to disasm bx_instruction_c instance (planned)

Huge patch. Almost all source files wre modified.
 2012-08-05 13:52:40 +00:00
Stanislav Shwartsman
4d03b57291 Allow larger quantum value for SMP simulations (up to 32) 
Update CHANGES
 2012-08-02 20:48:27 +00:00
Stanislav Shwartsman
d5c5c8e9e1 fixed bug produced by SVN commit rev11299 - missed case to clean 2012-08-02 20:43:14 +00:00
Stanislav Shwartsman
2e0f79d499 fixed compilation with AVX OFF but x86-64 on 2012-08-02 12:13:21 +00:00
Stanislav Shwartsman
b43ac7358e fixed typo-like bug in smm.cc 2012-08-01 14:56:51 +00:00
Stanislav Shwartsman
a1ebdc41ac Fixed SF bug [3548109] VMX State Not Restored After Entering SMM on 32-bit Systems 
Fixed .conf.nothing configure script

Fixed copyright for some files
 2012-07-27 08:13:39 +00:00
Stanislav Shwartsman
e0729e32b8 fixed bug 3548108 VMEXIT instruction length Not always getting updated 2012-07-26 16:03:26 +00:00
Stanislav Shwartsman
d9998269ef added branch_eip into near branch instructiontation callbacks 2012-07-24 15:32:55 +00:00
Stanislav Shwartsman
b225c158a9 fixed link error with no x86-64 2012-07-14 08:45:43 +00:00
Volker Ruppert
61292eb45b - missing SHELL fixes 2012-07-14 07:13:56 +00:00
Volker Ruppert
53438e92c6 - fixes based on Debian patches by Guillem Jover 
- set SHELL variable with configure script
  - add '--tag CXX' argument to libtool calls
 2012-07-14 07:01:43 +00:00
Stanislav Shwartsman
5d66e8450e implemented ADCX/ADOX instructions from rev013 of arch extensions published by Intel 2012-07-12 14:51:54 +00:00
Stanislav Shwartsman
bafde35c9c Intel Architecture 
Instruction Set Extensions
Programming Reference
rev013

was published including RDSEED and ADCX/ADOX instructions

add CPUID bits and VMX controls mentioned in the document
 2012-07-11 18:58:00 +00:00
Stanislav Shwartsman
ec06475dbf improve x86 hw breakpoint handling 2012-07-11 15:07:54 +00:00
Stanislav Shwartsman
58dde88887 VME is for CPU_LEVEL>=5 only 2012-07-08 18:16:25 +00:00
Stanislav Shwartsman
1964ef679a fixed compilation with x86-64 disabled 2012-07-01 14:46:27 +00:00
Stanislav Shwartsman
874ba7388d coding style change 2012-06-30 19:33:49 +00:00
Stanislav Shwartsman
39f3051ce5 fixed opcode primitive used for AVX instructions reading only half register (8byte) from the memory 2012-06-30 19:31:32 +00:00
Stanislav Shwartsman
16ecab5644 trying to guess real HW behavior for (V)DPPS/(V)DPPD instructions 2012-06-30 18:19:22 +00:00
Stanislav Shwartsman
f12396566c added CR8 to control registers print in debugger 2012-06-28 18:27:26 +00:00
Stanislav Shwartsman
3415f7bb0f add XD bit to page attributes print 2012-06-28 10:59:30 +00:00
Stanislav Shwartsman
79628a2f4f fixed VME corner case 2012-06-27 15:09:10 +00:00
Stanislav Shwartsman
4c38969ef0 fixed uninitialized variables 2012-06-24 17:52:45 +00:00
Stanislav Shwartsman
48ae41a2fd fixed MASKMOVDQU SSE instruction to match hardware 2012-06-23 16:25:52 +00:00
Stanislav Shwartsman
515d8b5c25 add new instrumentation callbacks for physical memory access from CPU 2012-06-18 11:41:26 +00:00
Stanislav Shwartsman
720a9b2fb7 fixed 64-bit segment print from internal debugger 2012-06-14 18:56:47 +00:00
Stanislav Shwartsman
171d400bd8 GATHER: update gather mask handling to match latest Intel SDM definition 
Fixes in x86 HW breakpoint handling
 2012-06-06 14:01:45 +00:00
Stanislav Shwartsman
6782efde05 correctly initialize lazy flags on reset 2012-06-05 20:53:22 +00:00
Stanislav Shwartsman
832d3a09a3 compile fix for SMP disable 2012-06-05 11:42:07 +00:00
Stanislav Shwartsman
a604818ecf fixed another valgrind issue 2012-06-05 11:40:59 +00:00
Stanislav Shwartsman
efcca3e9d4 fixup VCVTPH2PS instruction implementation to match published Intel SDM 2012-06-05 11:36:50 +00:00
Stanislav Shwartsman
37e193d49c clean one more valgrind issue 2012-06-04 19:21:23 +00:00
Stanislav Shwartsman
5192d09655 fixed some more valgrind issues 2012-06-04 18:46:07 +00:00
Stanislav Shwartsman
7bae496840 fixed valgrind issues in apic initialization and generic cpuid reported in SF bug report 2012-06-04 14:27:34 +00:00
Stanislav Shwartsman
bd6330d480 small optimization for debugger 2012-06-03 18:46:20 +00:00
Stanislav Shwartsman
2ee3386c37 cpu bugfixes 2012-05-31 14:25:49 +00:00
Stanislav Shwartsman
f528290652 fixed bug EPT Access Dirty support 2012-05-27 19:17:13 +00:00
Stanislav Shwartsman
8e7f582bc3 correct init.cc fix - copy/paste issue 2012-05-20 19:02:29 +00:00
Stanislav Shwartsman
3f32517201 small fix for save/restore 2012-05-20 18:58:57 +00:00
Stanislav Shwartsman
f9540f1c24 - Improved CPU status restore after restoring from Bochs saved image 
- Changed many BX_ERROR messages about VMX VMEXIT takesn to BX_DEBUG
 2012-05-19 20:36:40 +00:00
Stanislav Shwartsman
2644ef5f63 another had_vex/had_xop fix 2012-05-19 19:46:10 +00:00
Stanislav Shwartsman
59eb1318d5 small fix 2012-05-19 19:38:57 +00:00
Stanislav Shwartsman
ffc5e4bf2d optimize x2apic reg write 2012-05-12 19:07:18 +00:00
Stanislav Shwartsman
08d4655886 X2APIC: incorrect write to self IPI X2APIC register (with reserved bits set) should not trigger the self IPI 2012-05-12 12:49:05 +00:00
Stanislav Shwartsman
03162d86f5 LAPIC: fixed timer interrupts after reloading of LAPIC Timer Divide Configuration register 2012-05-12 11:52:29 +00:00
Stanislav Shwartsman
9ea0987396 fixed send_ipi case in x2apic 2012-05-12 08:07:30 +00:00
Stanislav Shwartsman
6180a0a733 remove unused leafs from generic_cpuid 2012-05-11 06:51:04 +00:00
Stanislav Shwartsman
b5c5082ff2 Completely remove b1() field from bxInstruction structure and resuse it for AVX instructions flags. 
the iaOpcode field has no masking anymore.

fixed bug during the code reorganization:
                        
+ XOP: Fixed instructions with operands order depending on VEX.W (fixed VEX.W read from instruction object)
 2012-05-11 06:35:16 +00:00
Volker Ruppert
53e1a5d204 - fixed typo (file names are case sensitive on Linux and others) 2012-05-08 18:33:26 +00:00
Stanislav Shwartsman
f01e5f3e11 removed b1() from shift methods in CPU - lead to removal of b1() field from bxInstruction_c 2012-05-08 16:42:15 +00:00
Stanislav Shwartsman
708fc666c8 Added Corei7 ivyBridge configuration to CPUDB 2012-05-07 12:31:22 +00:00
Stanislav Shwartsman
9d802e2762 very small cleanup 2012-05-05 18:40:37 +00:00
Stanislav Shwartsman
2188322ab3 fixed CR8 SVM intercepts 2012-05-03 16:12:58 +00:00
Stanislav Shwartsman
39c14ef0d1 Implemented EPT A/D extensions support. 
Bochs is fully aligned with the latest published revision of
Intel Architecture Manual (revision 043) now.
 2012-05-02 18:11:39 +00:00
Stanislav Shwartsman
e12494bf7b fixed segfault when setting ESP/EIP in GUI debugger 2012-04-16 19:18:23 +00:00