mirrors/Bochs
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
10,779 Commits 11 Branches 185 Tags 48 MiB
7ad7383fd2
Commit Graph

3084 Commits

Author SHA1 Message Date
Stanislav Shwartsman
7ad7383fd2 implement 256-wide SHUFF/SHUFI ops 2014-07-25 20:08:08 +00:00
Volker Ruppert
59eac1f196 Moved AVX/EVEX stuff to a new cpu subfolder and updated build system 
TODO: update MVSC workspace files
 2014-07-25 08:35:06 +00:00
Stanislav Shwartsman
9cc7b67369 bugfix 2014-07-22 20:49:58 +00:00
Stanislav Shwartsman
c4c8652a3b Implemented VPMOV?2? and VPMIN* AVX512 instructions 
The only missing AVX512BW/AVX512DQ opcodes are now:

"512.66.0F38.W1 10 VPSRLVW"
"512.66.0F38.W1 11 VPSRAVW"
"512.66.0F38.W1 12 VPSLLVW"

"512.66.0F3A.W1 0F VPALIGNR"
"NDS.66.0F3A.W0 42 VDBPSADBW"

"NDS.512.66.0F3A.W0 50 VRANGEPS
 NDS.512.66.0F3A.W1 50 VRANGEPD"
"NDS.512.66.0F3A.W0 51 VRANGESS
 NDS.512.66.0F3A.W1 51 VRANGESD"

"NDS.512.66.0F3A.W0 56 VREDUCEPS
 NDS.512.66.0F3A.W1 56 VREDUCEPD"
"NDS.512.66.0F3A.W0 57 VREDUCESS
 NDS.512.66.0F3A.W1 57 VREDUCESD"
 2014-07-22 20:36:55 +00:00
Stanislav Shwartsman
ad7ef68876 Implemented VMULLQ AVX512DQ instruction 
The only missing AVX512BW/AVX512DQ opcodes are now:

"512.66.0F38.W1 10 VPSRLVW"
"512.66.0F38.W1 11 VPSRAVW"
"512.66.0F38.W1 12 VPSLLVW"

"512.F3.0F38.W0 28 VPMOVM2B
 512.F3.0F38.W1 28 VPMOVM2W"
"512.F3.0F38.W0 29 VPMOVB2M
 512.F3.0F38.W1 29 VPMOVW2M"

"512.F3.0F38.W0 38 VPMOVM2D
 512.F3.0F38.W1 38 VPMOVM2Q"
"512.F3.0F38.W0 39 VPMOVD2M
 512.F3.0F38.W1 39 VPMOVQ2M"

"NDS.512.66.0F38.WIG 38 VPMINSB"
"NDS.512.66.0F38.WIG 3A VPMINUW"

"512.66.0F3A.W1 0F VPALIGNR"
"NDS.66.0F3A.W0 42 VDBPSADBW"

"NDS.512.66.0F3A.W0 50 VRANGEPS
 NDS.512.66.0F3A.W1 50 VRANGEPD"
"NDS.512.66.0F3A.W0 51 VRANGESS
 NDS.512.66.0F3A.W1 51 VRANGESD"

"NDS.512.66.0F3A.W0 56 VREDUCEPS
 NDS.512.66.0F3A.W1 56 VREDUCEPD"
"NDS.512.66.0F3A.W0 57 VREDUCESS
 NDS.512.66.0F3A.W1 57 VREDUCESD"
 2014-07-21 19:08:44 +00:00
Stanislav Shwartsman
009629f4d9 Implemented VEXTRACT* AVX512DQ instructions 
The only missing AVX512BW/AVX512DQ opcodes are now:

"512.66.0F38.W1 10 VPSRLVW"
"512.66.0F38.W1 11 VPSRAVW"
"512.66.0F38.W1 12 VPSLLVW"

"512.F3.0F38.W0 28 VPMOVM2B
 512.F3.0F38.W1 28 VPMOVM2W"
"512.F3.0F38.W0 29 VPMOVB2M
 512.F3.0F38.W1 29 VPMOVW2M"

"512.F3.0F38.W0 38 VPMOVM2D
 512.F3.0F38.W1 38 VPMOVM2Q"
"512.F3.0F38.W0 39 VPMOVD2M
 512.F3.0F38.W1 39 VPMOVQ2M"

"NDS.512.66.0F38.WIG 38 VPMINSB"
"NDS.512.66.0F38.WIG 3A VPMINUW"

"W1.NDS.512.66.0F38 40 VPMULLQ"

"512.66.0F3A.W1 0F VPALIGNR"
"NDS.66.0F3A.W0 42 VDBPSADBW"

"NDS.512.66.0F3A.W0 50 VRANGEPS
 NDS.512.66.0F3A.W1 50 VRANGEPD"
"NDS.512.66.0F3A.W0 51 VRANGESS
 NDS.512.66.0F3A.W1 51 VRANGESD"

"NDS.512.66.0F3A.W0 56 VREDUCEPS
 NDS.512.66.0F3A.W1 56 VREDUCEPD"
"NDS.512.66.0F3A.W0 57 VREDUCESS
 NDS.512.66.0F3A.W1 57 VREDUCESD"
 2014-07-20 20:46:48 +00:00
Stanislav Shwartsman
8108da227d bugfix in canonical violation detection 2014-07-20 18:19:02 +00:00
Stanislav Shwartsman
65ffcf5dc8 avoid using access_write_linear when not strickly needed 2014-07-19 20:01:44 +00:00
Stanislav Shwartsman
8ef5dcaca3 implement more avx512bw opcodes 2014-07-19 19:01:17 +00:00
Stanislav Shwartsman
7083e94077 implemented VBROADCAST*32x2 AVX512DQ opcodes 2014-07-19 18:36:38 +00:00
Stanislav Shwartsman
ca2859f449 implemented more AVX512BW opcodes 2014-07-19 13:30:54 +00:00
Stanislav Shwartsman
caad957384 bugfix in softfloat uint64_to_float64 conversion 2014-07-18 20:30:48 +00:00
Stanislav Shwartsman
3e8a5b99fa bugfix for vpsrldq opcode decoding 2014-07-18 20:08:10 +00:00
Stanislav Shwartsman
7a133766a8 implemented more AVX512BW opcodes 2014-07-18 19:40:27 +00:00
Stanislav Shwartsman
a556eb21fa implemented more AVX512BW opcodes 2014-07-18 16:28:44 +00:00
Stanislav Shwartsman
47e7e4adde bugfix in VFPCLASSPD implementation 2014-07-18 16:01:11 +00:00
Stanislav Shwartsman
48c508012f semantic fix 2014-07-18 12:35:17 +00:00
Stanislav Shwartsman
a06fba41ab commit new added files 2014-07-18 11:16:22 +00:00
Stanislav Shwartsman
94864fb9bc Implement AVX512BW and AVX512DQ extensions published in recently published Intel Archtecture Extensions manual rev20. 
https://software.intel.com/sites/default/files/managed/c6/a9/319433-020.pdf

Most of the instructions are implemented, more on the way.

+ few bugfixes for legacy AVX-512 emulation

AVX-512: Fixed bug in VCMPPS masked instruction implementation with 512-bit data size
AVX-512: Fixed AVX-512 masked convert instructions with non-k0 mask (behaved as non masked versions)
AVX-512: Fixed missed #UD due to invalid EVEX prefix fields for several AVX-512 opcodes (VFIXUPIMMSS/SD, FMA)
 2014-07-18 11:14:25 +00:00
Stanislav Shwartsman
0f39ce58be fixed compilation warnings and errors with MSVCPP 2014-07-09 16:08:16 +00:00
Stanislav Shwartsman
6ee7f48985 bugfix for VMX_VM_EXEC_CTRL1_EXTERNAL_INTERRUPT_VMEXIT control handling 2014-07-08 19:15:54 +00:00
Stanislav Shwartsman
816f5cc2d7 fixed massive code duplication 2014-07-03 06:40:42 +00:00
Stanislav Shwartsman
1e46de78ad add proper alignment of XMM/YMM/ZMM registers within CPU class 2014-06-25 19:12:14 +00:00
Stanislav Shwartsman
8e750e27c8 following many users requests - allow sandy bridge configuration even when AVX is not compiled in, just disable AVX in it 2014-06-06 18:29:28 +00:00
Stanislav Shwartsman
0b2364501d fixed compilation err when 3dnow is ON 2014-06-01 10:46:17 +00:00
Stanislav Shwartsman
d19727d75b updated AMD feature names in cpuid.h (taken from latest AMD software dev manuals) 2014-05-05 20:11:14 +00:00
Stanislav Shwartsman
2fe0aaa472 added configure option for trace linking optimization and mention it in CHANGES 2014-05-01 18:30:23 +00:00
Stanislav Shwartsman
8fbf673295 fixed compilation errors with FPU off 2014-04-29 18:49:38 +00:00
Stanislav Shwartsman
be6d2668c7 fixed comments in the code 2014-04-24 18:02:40 +00:00
Stanislav Shwartsman
be368f54d1 remove redundant type conversions 2014-03-23 20:01:58 +00:00
Stanislav Shwartsman
c079702a4d Finish softfloat implementation of float32/64_scalef. This checkin completes AVX-512 implementation. 2014-03-21 20:18:03 +00:00
Stanislav Shwartsman
1e7b6ff2cd check if XMM reg is clear using dedicated function 2014-03-17 20:50:59 +00:00
Stanislav Shwartsman
ab6230a9a8 Implemented XSAVEC instruction emulation and XINUSE optimization in the XSAVEOPT instruction 2014-03-17 20:29:44 +00:00
Stanislav Shwartsman
d8fa7aa28a implemented INIT optimization for XSAVEOPT instruction 2014-03-16 21:56:30 +00:00
Stanislav Shwartsman
72b715e5f0 fixed XSAVE to match spec, implemented first look into XINUSE. TODO: use XINUSE to optimize XSAVEOPT as well 2014-03-16 21:03:13 +00:00
Stanislav Shwartsman
97d2965d58 continue xsave code rework 2014-03-16 20:37:47 +00:00
Stanislav Shwartsman
9d8d895b52 cpuid fixes 2014-03-15 20:19:30 +00:00
Stanislav Shwartsman
378e7e16eb fixed major code duplication in CPUDB classes 2014-03-15 19:24:42 +00:00
Stanislav Shwartsman
d18cabc7a9 add new CPUDB files 2014-03-15 18:31:33 +00:00
Stanislav Shwartsman
c87605722b CPUDB: added AMD Trinity to the database 2014-03-15 18:30:13 +00:00
Stanislav Shwartsman
d10fa93d89 fixed to VSCALEF instruction + one more step in the implementation in the softfloat 2014-03-14 20:26:50 +00:00
Stanislav Shwartsman
08f5383831 fix for x87 2014-03-09 22:06:13 +00:00
Stanislav Shwartsman
02e19de346 Added shape of implementation for last missing VSCALEF* AVX-512 instructons. 
The softfloat implementation is still missing (only corner cases are supported).
Extend softfloat floatNN_class methods to distinguish between SNaN and QNaN.
 2014-03-09 21:42:11 +00:00
Stanislav Shwartsman
211208dc30 zero masking is not allowed for all forms of vsib, including gather 2014-03-08 20:27:10 +00:00
Stanislav Shwartsman
48ab171b79 enumerate possible fetchdecode failures leading to #UD decoding. TODO: add this info to BX_IA_ERROR as immediate 2014-03-08 20:09:00 +00:00
Stanislav Shwartsman
069498eef6 zero masking is not allowed for mem destination instructions 2014-03-08 19:49:35 +00:00
Stanislav Shwartsman
bfe6ecabb8 xsave sse state using same interface as all other advanced states 2014-03-04 21:06:29 +00:00
Stanislav Shwartsman
39bb48cd69 added missing includes 2014-03-02 19:18:05 +00:00
Stanislav Shwartsman
c544e82c43 fixed code duplication in BEXTR implementations 2014-03-02 19:16:13 +00:00
Stanislav Shwartsman
bc5af269b7 Fix some more code duplication with sclaar_arith.h 
Do not clear IA32_FEATURE_CTRL MSR on soft reset (will clear the VMX lock bit)
On real HW XSAVE/XRSTOR which is not 4-byte aligned cause #AC(0) intead of #GP(0) when alignment check is enabled
 2014-03-02 16:40:13 +00:00