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87 Commits

Author SHA1 Message Date
Stanislav Shwartsman
c8cd1f805a Enabled LAHF/SAHF for x86-64 mode 2006-01-17 19:50:42 +00:00
Stanislav Shwartsman
e2a5b9c338 MOV to/from test register are UD in x86-64 2005-11-11 22:02:42 +00:00
Stanislav Shwartsman
cb4ec526ab Fix comments and cleanup ... 
No functional change
 2005-11-11 21:34:57 +00:00
Stanislav Shwartsman
38a7e0abea 0f 0d (3dnow prefetch instruction) should execute as NOP when running on Intel EM64T CPU and as prefetch on AMD 2005-11-11 21:09:02 +00:00
Stanislav Shwartsman
d1c722211e Fix duplicate opcodes, fix opcode names and disasm bugs 2005-09-23 16:45:41 +00:00
Stanislav Shwartsman
37bd193337 Split PUSHF/POPF to 3 different methods according to op size. 
By the way fix VIP/VIF flags handling in POPF/PUSHF (future fix for VME)
 2005-08-08 19:56:11 +00:00
Stanislav Shwartsman
f096a80716 Fix code duplication for check_cs descriptor 
The function will execute
 - segment is executable code segment
 - conforming/non-conforming segment priviledge checks
 - segment is present
 2005-08-01 21:40:17 +00:00
Stanislav Shwartsman
954aae3f99 Speedup push/pop operations, they actually not needed to do can_push/can_pop checkes, the same checkes already done in read/write_virtial methods 
Split push_seg_reg methods according to op size
 2005-07-31 17:57:27 +00:00
Stanislav Shwartsman
2b5a812674 Split last bit.cc methods according to os16/32/64 2005-07-25 04:18:20 +00:00
Stanislav Shwartsman
ce8f1ade07 Some not really significant speedups 2005-06-21 17:01:21 +00:00
Stanislav Shwartsman
015ad92958 Added SMP status to TODO file 
Removed abusive BX_INFO from WBINVD instruction
The PREFETCHW (3DNow!) instruction should not #UD in x86-64 even on Intel w/o 3DNow!
 2005-05-27 01:53:38 +00:00
Stanislav Shwartsman
663f7d5ef3 CMPXCHG16B instruction implemented 2005-05-19 20:25:16 +00:00
Stanislav Shwartsman
a86002a8bc Improve Bochs instrumentation 
Small changes in APIC timer, should fix the bug report
[ 957660 ] >>PANIC<< APIC: R(curr timer count): delta < initial
 2005-04-29 21:28:59 +00:00
Stanislav Shwartsman
619942cf9a Enable SYSENTER/SYSEXIT together with x86-64 support, these instructions used by gentoo amd64 LiveCD image (at least it WRMSR to SYSENTER MSRs). 
SYSENTER/SYSEXIT is not recognized in long mode but it could be used i any other mode without problem
 2005-03-29 21:59:44 +00:00
Stanislav Shwartsman
e6e9dd3825 Extend Bochs instrumentation 
Compatability fixes
 2005-03-17 20:50:57 +00:00
Stanislav Shwartsman
709b218c10 Reduce metaInfo initialization in fetchDecode 2005-03-01 21:44:01 +00:00
Stanislav Shwartsman
2bfc842c09 CPU fixes by Kevin Lawton 2005-02-16 21:27:21 +00:00
Stanislav Shwartsman
9492942ae6 In 64-bit mode, the CS, DS, ES, and SS segment overrides are ignored. 2005-02-12 19:25:33 +00:00
Stanislav Shwartsman
f375203fdb preparations for x86-64 support in disasm 2004-12-12 22:12:43 +00:00
Stanislav Shwartsman
46bb3d8853 remove duplicated data arrays from CPU 2004-12-11 20:51:13 +00:00
Stanislav Shwartsman
5213e903bd mov duplicate opcode groups from fectchdecode*.cc to .h 
use common register accessor macroses instead of direct register file structure access
 2004-11-26 20:21:28 +00:00
Stanislav Shwartsman
69c0b06955 fixes in disassembler 
split REPEAT instructions according to opsize to speedup execution
now each REPEATABLE instruction splitted to 3 different instructions, one for 16-bit operand size, one for 32-bit and one for 64-bit. Choosing of correct instruction occure in fetchdecode step.
 2004-11-20 23:26:32 +00:00
Stanislav Shwartsman
730b8c0243 Fix this pointers in the code 2004-11-14 21:25:42 +00:00
Stanislav Shwartsman
4f1f070c37 Fix comments for code 2004-10-08 19:29:04 +00:00
Stanislav Shwartsman
3adc5c8659 Fix lock prefix for XOR instruction in 64-bit mode 2004-10-08 19:07:18 +00:00
Stanislav Shwartsman
760a195c9d * Fix LOCK prefix handling for x86-64 
* Split BT*_EvGv functions to 3 different function according to exec mode
 2004-09-17 20:47:19 +00:00
Stanislav Shwartsman
fc631037ff remove obsolete comments from fetchdecode 2004-09-06 20:22:39 +00:00
Stanislav Shwartsman
279d207d45 Fix fetchdecode bugs reported by Gilbert Netzer 
(opcode patches for x86_64 cpu)
 2004-05-03 17:58:36 +00:00
Stanislav Shwartsman
0eb71999db Added missed 287 opcodes which should be executed as NOP in 387+ 2003-12-28 18:19:41 +00:00
Stanislav Shwartsman
9ccb363ec3 bochs style decode/execute of FPU instructions. 
With this coding style each instruction could be implemented separatelly even not together with current Bochs FPU emulator.
Step-by-step I am going to transfer all FPU instructions from current Bochs FPU emulator to new style and remove an old bugged emulator.
Anyway, now I could implement all currently missed FPU instructions without hacking wm-fpu-emu.
 2003-12-27 13:50:06 +00:00
Stanislav Shwartsman
ac20b6405a - FXSAVE/FXRSTOR instructions should be available in P6 mode 
- Added second UD2 opcode to fetchdecode
- Added RDPMC instruction to fetchdecode
- 'changes' updated
 2003-10-24 18:34:16 +00:00
Stanislav Shwartsman
7f570b0150 Added PNI new streaming extensions instructions 
PNI could be enabled by setting BX_SUPPORT_PNI in config.h
After the feature will be fully validation I'll also add configure option.

The implemntation is ~complete. I've missed only three FPU new opcodes of FUSTTP instruction and MONITOR/WAIT instructions.

Enjoy ! ;)
 2003-08-29 21:20:52 +00:00
Stanislav Shwartsman
254ad17328 Changes method of resolving opcode/attributes from group table 
New method more flexible and easy to understanding.
Reorganizing fetchdecode code and make it more easy and understandable
 2003-08-28 19:25:23 +00:00
Stanislav Shwartsman
f6711d51f2 Fixed very serious bug in x86-64 with wrong decoding of opcodes with two immediates 2003-08-15 13:17:16 +00:00
Stanislav Shwartsman
3c00944998 I hope this is the last one ... 2003-05-29 19:44:59 +00:00
Stanislav Shwartsman
56cc6469e3 Ops, missed one ... 2003-05-29 17:19:38 +00:00
Stanislav Shwartsman
f933d604d3 Fixed missed BxLockable for XCHG instruction 2003-05-29 17:15:08 +00:00
Stanislav Shwartsman
140ff2541b Ability to configure x86-64 without 3DNOW 2003-05-21 15:20:51 +00:00
Stanislav Shwartsman
1d45167e5b Merged NEW-INSTRUCTIONS branch 2003-05-15 16:41:17 +00:00
Christophe Bothamy
83b8bbedff - fix REX MOVB immediate for x86_64 (patch by Arnd Bergmann) 
(bug [ 720776 ] REX MOVB immediate broken for x86_64)
 2003-04-26 10:02:03 +00:00
Stanislav Shwartsman
446fca9ed0 Superfluous braces in initializers in fetchdecode.cc 2003-04-23 17:52:59 +00:00
Stanislav Shwartsman
40bd4f138b Little style changes 
Elliminated i387_t alimit field (not used in FPU)
 2003-04-16 18:38:53 +00:00
Stanislav Shwartsman
1d54caca9b Fixed compilation error 2003-04-09 19:20:05 +00:00
Stanislav Shwartsman
7db893970c Read attributes bits even for BxSplit11b opcodes 
Move lock prefix check later in fetchdecode function when all attributes is ready.
 2003-04-06 19:08:31 +00:00
Stanislav Shwartsman
1e71c9e56e Merged patch-unallowed-lock-cases patch. 
According to the Intel manuals:

  The  LOCK  prefix  can be prepended only to the following instructions
  and  only  to  those  forms  of the instructions where the destination
  operand  is  a  memory operand: ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG,
  CMPXCH8B,  DEC,  INC,  NEG, NOT, OR, SBB, SUB, XOR, XADD, and XCHG. If
  the  LOCK prefix is used with one of these instructions and the source
  operand  is a memory operand, an undefined opcode exception (#UD) will
  be  generated. An undefined opcode exception will also be generated if
  the  LOCK  prefix  is used with any instruction not in the above list.

 Checking of the LOCK prefix done in fetchDecode state and not overloads
 Bochs's execution.
 2003-04-05 12:16:53 +00:00
Christophe Bothamy
1a518b81fe - add __attribute__((regparm(X))) performance trick with gcc on x86 
on some cpu instructions (patch from Conn Clark)
- performance improvement is 1% on win95 boot
 2003-03-17 00:41:01 +00:00
Peter Tattam
2f9088a223 x86-64 emulation. 
Fixed IRETD in 64 bit mode
 2003-03-13 00:45:44 +00:00
Stanislav Shwartsman
cdfc3cbce4 instrumentation enchancements: 
* renamed CPU_ID to BX_CPU_ID.
  with this new name there is no possibility for name contentions and BX_CPU_ID
  definition could be moved out to NEED_CPU_REG_SHORTCUTS block

* returned back `unsigned BX_CPU::which_cpu(void)` function

* added BX_CPU_ID parameter for
	BX_INSTR_PHY_READ(a20addr, len);
	BX_INSTR_PHY_WRITE(a20addr, len);
    now it will be
	BX_INSTR_PHY_READ(cpu_id, a20addr, len);
	BX_INSTR_PHY_WRITE(cpu_id, a20addr, len);
 2003-02-13 15:04:11 +00:00
Peter Tattam
22d855a6c0 Fixed wrong RETF instructions for 64 bit mode. 2003-02-08 05:51:38 +00:00
Stanislav Shwartsman
4b59ecbc62 Implemented SSE/SSE2 duplicate opcodes in more intellegent way ... 2002-12-22 21:48:23 +00:00