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767 Commits

Author SHA1 Message Date
Stanislav Shwartsman
b69f728246 Fixed internal debugger part of the bug: 
#3312237 stepN command might be not working properly
The problem still can be exists for SMP.
 2011-08-17 19:51:32 +00:00
Stanislav Shwartsman
6606c62439 cr4 available since Pentium only 2011-08-16 16:49:04 +00:00
Stanislav Shwartsman
6344c6a719 Added P2 Klamath CPUID + some code reorg again 2011-08-11 18:06:09 +00:00
Stanislav Shwartsman
f15bc6cf75 support for NX outside of x86-64. 
required for Intel Yonah processor which is another interesting CPUID to be added
also found Via C7 CPUID, looking for the way to add it too
 2011-08-10 22:04:33 +00:00
Stanislav Shwartsman
1b27438146 cleanups + small code reorg 2011-08-10 20:31:29 +00:00
Stanislav Shwartsman
360481b391 infastructure for RDMSR/WRMSR control for cpuid class 
now the order is going to be:

1. MSRs emulated in Bochs (msr.cc)
2. MSRs emulated in model specific derivative class of cpuid_t
3. MSR can be loaded from msrs.def file
4. MSR is not found. We can fault or ignore based on ignore_bad_msrs option
 2011-08-09 22:11:56 +00:00
Stanislav Shwartsman
2ee0029749 extract ffxsr support to separate CPU feature 2011-08-04 19:02:49 +00:00
Stanislav Shwartsman
075db389a9 added atom n270 cpuid + small fixes 2011-08-03 17:49:49 +00:00
Stanislav Shwartsman
e48765a511 VMX fixed, cleanups 2011-07-29 20:22:35 +00:00
Stanislav Shwartsman
4ac67ec386 compilation when cu_level < 4 2011-07-29 15:24:32 +00:00
Stanislav Shwartsman
78327d3e5e First step toward completely configurable CPU. 
Change CPUID to generic interface which could be chosen from .bochsrc.
Bochs CPU emulation will enable/disable features (like instruction sets) according to CPUID that is selected.
TODO: Add database of CPUID from real hardware CPUs
 2011-07-28 16:17:42 +00:00
Stanislav Shwartsman
d11114ac19 Patch for emulating target with larger memory than host has available by Gary Cameron. 
The patch was posted in mailing list at Thu 6/16/2011.

Desription for CHANGES:

- Memory
  - Added new configure option which enables RAM file backing for large guest
    memory with a smaller amount host memory, without causing a panic when
    host memory is exhausted (patch by Gary Cameron). To enable configure with
        --enable-large-ramfile option.
 2011-07-22 17:46:06 +00:00
Stanislav Shwartsman
b4118fcbfe correct natural width VMX field read/write len 2011-07-21 20:58:54 +00:00
Stanislav Shwartsman
a69eeb13f3 move cpuid defs to cpuid.h 2011-07-19 21:14:07 +00:00
Stanislav Shwartsman
cddd1e3758 MONITOR/MWAIT: Do monitor on cache line granularity only + bugfix with possible TLB caching of monitored line 2011-07-18 21:44:22 +00:00
Stanislav Shwartsman
002c86660a reword all the CPU code in preparation for future CPU speedup implementation. 
Bochs emulation can be another 10-15% faster using technique described in paper
"Fast Microcode Interpretation with Transactional Commit/Abort"
http://amas-bt.cs.virginia.edu/2011proceedings/amasbt2011-p3.pdf
 2011-07-06 20:01:18 +00:00
Stanislav Shwartsman
909e750549 Implemented VMX preemption timer VMEXIT control (patch by Jianan Hao) 2011-07-03 15:59:48 +00:00
Stanislav Shwartsman
08ba847ce4 fix bug inserted with prev commit + cleanup 2011-06-28 16:04:40 +00:00
Stanislav Shwartsman
87953711b1 cleanup in mmx code 2011-06-26 19:31:42 +00:00
Stanislav Shwartsman
2f582db722 compile less stuff for cpu-level=5 2011-06-26 19:15:30 +00:00
Stanislav Shwartsman
beafa7c88b improved x86 hw code bp handling 2011-06-24 13:38:34 +00:00
Stanislav Shwartsman
31be835056 bugfix + rename function 2011-06-14 19:56:28 +00:00
Stanislav Shwartsman
ef38c9e235 fix decode for VCVTPH2PS 2011-06-11 18:26:05 +00:00
Stanislav Shwartsman
8399dee24c implemented AVX float16 convert instructions 2011-06-11 13:12:32 +00:00
Stanislav Shwartsman
3f075d1ddf disasm for invpcid 2011-06-10 12:49:52 +00:00
Stanislav Shwartsman
29e3f6e762 remove trace cache disabled mode from the code. next step going to be - introducing new optimization features based on trace cache 2011-06-01 20:34:04 +00:00
Stanislav Shwartsman
04e9254e2c AMD released new Vol4: 128 and 256 bit vector instructions, dropped SSE4A 2011-05-30 20:15:50 +00:00
Stanislav Shwartsman
ee3f9e36cb Implemented Supervisor Mode Execution Protection (SMEP) 2011-05-29 16:28:26 +00:00
Stanislav Shwartsman
de95fa8e13 more changes towards configurable cpuid 2011-05-24 18:23:28 +00:00
Stanislav Shwartsman
92bb77ef1d Merge patch from SF tracker: 
[3298173] Breakpoint on VMEXIT event by Jianan Hao

Patch description:

The patch provides a new command "vmexitbp" to set breakpoint when VM guest exit. The simulation will be stopped before first HOST mode instruction is executed.

Usage:
Type "vmexitbp" in debugger command window to switch it on/off (similar to modebp).


Currently, the patch has no corresponding interface on GUI debugger. Someone may add it if interested.
 2011-05-06 08:19:03 +00:00
Stanislav Shwartsman
a02ddb36d2 undo a change from 2 weeks ago that cause correctness failure 2011-05-06 08:03:45 +00:00
Stanislav Shwartsman
c44f82f4ac small cleanup 2011-04-25 20:26:22 +00:00
Stanislav Shwartsman
a02d8cfe67 cleanups, simplications, copyright updates 2011-04-23 20:39:27 +00:00
Stanislav Shwartsman
4f46b6eab2 bcd flags handling change 2011-04-23 10:49:36 +00:00
Stanislav Shwartsman
a1b523dacd warning fix 2011-04-22 15:18:05 +00:00
Stanislav Shwartsman
5230bd27ee added/fixed comments 2011-04-21 15:51:36 +00:00
Stanislav Shwartsman
024a1ace38 move X2APIC to be .bochsrc option, rework of the cpuid code 2011-04-21 13:27:42 +00:00
Stanislav Shwartsman
6e79fdfb1e optimize data hw breakpoint 2011-04-09 05:12:28 +00:00
Stanislav Shwartsman
4de76b0571 introduced victim cache for a trace cache structure. 
Allows to significantly  cut trace cache miss latenct and find data in victim cahe instead of redoding it 
8 entries VC in parallel with direct map 64K entries
 2011-03-25 23:06:34 +00:00
Stanislav Shwartsman
dd36d3c754 fixed code breakpoint hit 2011-03-24 19:06:58 +00:00
Stanislav Shwartsman
31dd6a70db small cleanups 2011-03-20 21:16:45 +00:00
Stanislav Shwartsman
7664c55b08 first fixups after AVX 
(and for AVX)
 2011-03-20 18:27:31 +00:00
Stanislav Shwartsman
7ced718040 implemented AVX instructions support 
many changes - some cleanup will follow
please report ay found bugs !
 2011-03-19 20:09:34 +00:00
Stanislav Shwartsman
16021a0ddb rename model_specific.h to be cpuid.h 2011-03-19 17:35:18 +00:00
Stanislav Shwartsman
63fe52f601 accessors for DR6 and DR7 fields 2011-03-15 20:20:15 +00:00
Stanislav Shwartsman
edd7c2d787 small reorg in cpuid code 2011-03-14 20:28:16 +00:00
Stanislav Shwartsman
acd320699d small cleanups 2011-03-14 06:25:54 +00:00
Stanislav Shwartsman
2bef4597d6 volatile is redundant here 2011-03-03 19:51:29 +00:00
Stanislav Shwartsman
acb83acfa7 Fixed decoding of CRC32 instr 2011-02-26 20:43:11 +00:00
Stanislav Shwartsman
66682a0ba7 added ability to configure CPU family and model through .bochsrc 2011-02-25 15:05:48 +00:00