Commit Graph

169 Commits

Author SHA1 Message Date
Stanislav Shwartsman
b69345225b Correct model_id for Pentium MMX in CPUID 2005-02-13 21:20:48 +00:00
Stanislav Shwartsman
68714924b0 Return local APIC id in CPUID 00000001h function in EBX register 2005-01-29 15:24:57 +00:00
Stanislav Shwartsman
57fcc89274 Non-Execution support impelemented and enabled in CPUID when in x86-64 configuration 2005-01-20 19:37:43 +00:00
Stanislav Shwartsman
8fe15b0ddc Fixed compilation error 2004-12-17 10:50:49 +00:00
Stanislav Shwartsman
5955549a8d Fixed bug report [#879050]
Bochs reports enabled APIC without support
2004-12-14 20:41:55 +00:00
Stanislav Shwartsman
7b62a6e206 Fix reset registers in CPU for #RESET signal
Extract ICACHE from cpu.h to separate icache.h
2004-11-14 19:29:34 +00:00
Stanislav Shwartsman
5e23909c7c prepations for NX bit implementation 2004-10-21 18:20:40 +00:00
Stanislav Shwartsman
a28a2c6ce1 Added comments 2004-10-03 20:25:19 +00:00
Stanislav Shwartsman
c9bc4eaf02 1. add comments to CPUID instruction
2. small cleanup
2004-09-26 20:29:04 +00:00
Stanislav Shwartsman
b6657b1322 NX feature still not implemented in Bochs.
The change forces CPUID do not report bit 20 (NX bit support)
May be some OS that really checks it will boot better now
2004-09-17 21:01:50 +00:00
Stanislav Shwartsman
016207b222 Commented problematic check in misc_mem.cc
Implemnted lazy-flags and undocumented flags handling for IMUL instructions
2004-08-30 21:47:24 +00:00
Stanislav Shwartsman
27897c925e Fix undocumented flags handling for SHL instruction
remove invalidate_prefetch_q from CPUID
2004-08-27 18:43:23 +00:00
Stanislav Shwartsman
f3730cd784 Implemented two last SSE instructions RSQRTSS and RSQRTPS
MSDEV workspaces updated with new file
CPUID will detect and CPU will execute FXSAVE/FXRSTOR instructions when cpu-level-hacked=6 and not only when cpu-level=6
2003-12-31 17:35:43 +00:00
Christophe Bothamy
e3bec02532 - fix bug preventing x86-64 detection 2003-12-30 14:14:28 +00:00
Stanislav Shwartsman
ac20b6405a - FXSAVE/FXRSTOR instructions should be available in P6 mode
- Added second UD2 opcode to fetchdecode
- Added RDPMC instruction to fetchdecode
- 'changes' updated
2003-10-24 18:34:16 +00:00
Stanislav Shwartsman
9690ed763b // is not allowed in pure-C 2003-10-05 12:14:02 +00:00
Stanislav Shwartsman
b50fb9e76e code simplification before FPU development
print if Bochs supports 3DNOW to log file
2003-09-27 20:58:46 +00:00
Stanislav Shwartsman
15e84d0f5d dos2unix fixes 2003-09-26 16:07:38 +00:00
Stanislav Shwartsman
789db2603e Added P4 support to CPUID instruction
Extracted CPUIS instructions to separate file
2003-09-26 15:32:41 +00:00