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Fixed bug report [#879050]

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Bochs reports enabled APIC without support
This commit is contained in:
Stanislav Shwartsman 2004-12-14 20:41:55 +00:00
parent d5684940a1
commit 5955549a8d
5 changed files with 28 additions and 24 deletions
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14
bochs/cpu/apic.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: apic.cc,v 1.35 2004-11-04 22:41:23 sshwarts Exp $
// $Id: apic.cc,v 1.36 2004-12-14 20:41:55 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
#define NEED_CPU_REG_SHORTCUTS 1
@ -19,10 +19,6 @@ bx_generic_apic_c::bx_generic_apic_c ()
hwreset ();
}
bx_generic_apic_c::~bx_generic_apic_c ()
{
}
void bx_generic_apic_c::set_arb_id (int new_arb_id)
{
// politely ignore it. This gets sent to every APIC, regardless of its type.
@ -88,8 +84,7 @@ bx_bool bx_generic_apic_c::is_selected (Bit32u addr, Bit32u len)
return false;
}
void
bx_generic_apic_c::read (Bit32u addr, void *data, unsigned len)
void bx_generic_apic_c::read (Bit32u addr, void *data, unsigned len)
{
if ((addr & ~0xf) != ((addr+len-1) & ~0xf))
BX_PANIC(("APIC read spans 32-bit boundary"));
@ -405,11 +400,6 @@ BX_CPU_C *bx_local_apic_c::get_cpu (Bit8u id)
return cpu;
}
bx_local_apic_c::~bx_local_apic_c(void)
{
// nothing for now
}
void bx_local_apic_c::set_id (Bit8u newid)
{
bx_generic_apic_c::set_id (newid);

4
bochs/cpu/apic.h
View File

@ -50,7 +50,7 @@ protected:
#define APIC_UNKNOWN_ID 0xff
public:
bx_generic_apic_c ();
virtual ~bx_generic_apic_c ();
virtual ~bx_generic_apic_c () { }
virtual void init ();
virtual void hwreset () { }
Bit32u get_base (void) const { return base_addr; }
@ -139,7 +139,7 @@ class BOCHSAPI bx_local_apic_c : public bx_generic_apic_c
public:
bx_bool INTR;
bx_local_apic_c(BX_CPU_C *mycpu);
virtual ~bx_local_apic_c(void);
virtual ~bx_local_apic_c(void) { }
BX_CPU_C *cpu;
virtual void hwreset ();
virtual void init ();

5
bochs/cpu/cpuid.cc
View File

@ -145,7 +145,10 @@ Bit32u get_std_cpuid_features()
#if BX_CPU_LEVEL >= 6
features |= (1<<15); // Implement CMOV instructions.
#if BX_SUPPORT_APIC
features |= (1<< 9); // APIC on chip
// if MSR_APICBASE APIC Global Enable bit has been cleared,
// the CPUID feature flag for the APIC is set to 0.
if (BX_CPU_THIS_PTR msr.apicbase & 0x800)
features |= (1<< 9); // APIC on chip
#endif
#if BX_SUPPORT_SSE >= 1
features |= (1<<25); // support SSE

10
bochs/cpu/init.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: init.cc,v 1.62 2004-12-11 20:51:13 sshwarts Exp $
// $Id: init.cc,v 1.63 2004-12-14 20:41:55 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -162,7 +162,7 @@ cpu_param_handler (bx_param_c *param, int set, Bit64s val)
void BX_CPU_C::init(BX_MEM_C *addrspace)
{
BX_DEBUG(( "Init $Id: init.cc,v 1.62 2004-12-11 20:51:13 sshwarts Exp $"));
BX_DEBUG(( "Init $Id: init.cc,v 1.63 2004-12-14 20:41:55 sshwarts Exp $"));
// BX_CPU_C constructor
BX_CPU_THIS_PTR set_INTR (0);
#if BX_SUPPORT_APIC
@ -782,7 +782,11 @@ void BX_CPU_C::reset(unsigned source)
/* APIC Address, APIC enabled and BSP is default, we'll fill in the rest later */
BX_CPU_THIS_PTR msr.apicbase = APIC_BASE_ADDR;
BX_CPU_THIS_PTR msr.apicbase <<= 12;
#if BX_SUPPORT_APIC
BX_CPU_THIS_PTR msr.apicbase |= 0x900;
#else
BX_CPU_THIS_PTR msr.apicbase |= 0x100;
#endif
#if BX_SUPPORT_X86_64
BX_CPU_THIS_PTR msr.lme = BX_CPU_THIS_PTR msr.lma = 0;
#endif
@ -844,7 +848,7 @@ void BX_CPU_C::reset(unsigned source)
async_event = 1;
}
#else
BX_CPU_THIS_PTR async_event=2;
BX_CPU_THIS_PTR async_event=2;
#endif
BX_CPU_THIS_PTR kill_bochs_request = 0;

19
bochs/cpu/proc_ctrl.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: proc_ctrl.cc,v 1.87 2004-11-14 21:25:42 sshwarts Exp $
// $Id: proc_ctrl.cc,v 1.88 2004-12-14 20:41:55 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -1521,7 +1521,7 @@ void BX_CPU_C::RDMSR(bxInstruction_c *i)
invalidate_prefetch_q();
if (v8086_mode()) {
BX_INFO(("RDMSR: Invalid whilst in virtual 8086 mode"));
BX_INFO(("RDMSR: Invalid in virtual 8086 mode"));
goto do_exception;
}
@ -1652,7 +1652,7 @@ void BX_CPU_C::WRMSR(bxInstruction_c *i)
invalidate_prefetch_q();
if (v8086_mode()) {
BX_INFO(("WRMSR: Invalid whilst in virtual 8086 mode"));
BX_INFO(("WRMSR: Invalid in virtual 8086 mode"));
goto do_exception;
}
@ -1705,11 +1705,18 @@ void BX_CPU_C::WRMSR(bxInstruction_c *i)
12:35 APIC Base Address
36:63 Reserved
*/
#if BX_SUPPORT_APIC
case BX_MSR_APICBASE:
BX_CPU_THIS_PTR msr.apicbase = ((Bit64u) EDX << 32) + EAX;
BX_INFO(("WRMSR: wrote %08x:%08x to MSR_APICBASE", EDX, EAX));
if (BX_CPU_THIS_PTR msr.apicbase & 0x800)
{
BX_CPU_THIS_PTR msr.apicbase = ((Bit64u) EDX << 32) + EAX;
BX_INFO(("WRMSR: wrote %08x:%08x to MSR_APICBASE", EDX, EAX));
}
else {
BX_INFO(("WRMSR: MSR_APICBASE APIC global enable bit cleared !"));
}
return;
#endif
#if BX_SUPPORT_X86_64
case BX_MSR_EFER: