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128 Commits

Author SHA1 Message Date
Stanislav Shwartsman
ae61538847 create classes for Vmexec controls for robustness 2024-01-27 18:04:00 +02:00
Stanislav Shwartsman
f8d1050a3f
Implemented SVM VM_CR_MSR and INIT redirection feature (#220) 
Save and restore SVM MSRs
 2024-01-16 07:42:28 +02:00
Stanislav Shwartsman
0eab037907 dynamically allocate VMCB_CACHE only if SVM is actually enabled by CPU model 
also reduces include dependency on svm.h
 2024-01-12 00:56:09 +02:00
Stanislav Shwartsman
3a02e85599
AMX support (#212) 2024-01-10 20:13:25 +02:00
Shwartsman
a67fb31d4f LA57: attempt to change (not just clear) LA57 in long mode cause #GP 2024-01-05 18:46:56 +02:00
Shwartsman
41c2bb8bee fix for LA57 cr4 checks, thanks Ben for pointing this out 2024-01-04 08:35:33 +02:00
Stanislav Shwartsman
ec7ef85ed9 exclude cpuid.h from cpu.h to reduce compilation dependency 2023-12-29 21:27:24 +02:00
Stanislav Shwartsman
e3612c30f8 Implement support for LA57 and 5-level paging 2023-12-29 14:48:38 +02:00
Stanislav Shwartsman
e7f2450220 fix XSAVE leaf resporting in CPUID 2023-12-24 20:12:30 +02:00
Shwartsman
fc919cd132 use true/false instead of 0/1 for bool in the cpu code 2023-12-19 20:44:56 +02:00
Shwartsman
d794b516e1 rewrite XSAVE/XRESTORE CPUID leaf reporting, 
fixed several bugs and made code correct for all future XSAVE extensions
 2023-12-18 11:35:55 +02:00
Shwartsman
3c857f2ad1 make APIC from static object to dynamic so many cc files won't need to be dependent on apic.h 2023-11-28 11:08:42 +02:00
Stanislav Shwartsman
a5c6bcfd15 remove in_repeat variable and replace it with correct EFLAGS.RF management 2023-11-27 13:51:25 +02:00
Stanislav Shwartsman
280303d76c
initial code for UINTR implementation (#138) 
First step into implementing UINTR - User Level Interrupts ISA extension
To be continued

---------

Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2023-11-25 16:43:47 +02:00
Shwartsman
62c2c877d0 rename VMEXIT controls in Bochs code to match their actual names and meaning 2023-11-23 19:58:08 +02:00
Shwartsman
bd4cb7ffa6 fixed compilation without SVM configured in 2023-11-20 19:10:46 +02:00
Stanislav Shwartsman
a3fe8c2c8d introduce get_efer_allow_mask function to avoid placing that code directly in init.cc 2023-11-17 23:40:28 +02:00
Stanislav Shwartsman
b78e93c9e3 optimize handling of allowed_to_run_FPU_MMX instructios common block 
now checked at decode and not at every instruction
simpler code and also 1% faster winXP boot time as bonus
other x87 and mmx heavy guests may benefit even more
 2023-11-08 06:48:53 +02:00
Stanislav Shwartsman
8316d7698f
implemented Linear Address Separation extension (LASS) (#90) 
Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2023-10-15 14:32:01 +03:00
Stanislav Shwartsman
1e4f1624c8 remove trailing whitespace from source files 2022-08-23 21:46:04 +03:00
Stanislav Shwartsman
08a068a161 fixed SVM V_TPR handling SF bug #1428 AMD SVM Hyper-V fails 2021-03-11 21:19:45 +00:00
Stanislav Shwartsman
c87ce2d11a fixed some MSVC wannings in CPU code 2021-02-08 13:06:44 +00:00
Stanislav Shwartsman
1bf18b8aae ! CPUID: Added TigerLake CPU definition (features CET and CLWB support) 
- CPU code refactor, remove uses of bx_bool datatype and use C++ classic bool instead.
  This enable better compiler optimizations and reduce binary size
 2021-01-30 08:35:35 +00:00
Stanislav Shwartsman
c6050a99d1 implemented AVX encoded VNNI instructions published in recent SDM - not tested yet 2020-10-03 09:23:28 +00:00
Stanislav Shwartsman
4023b640d6 Protection Keys: Implemented Supervisor-Mode Protection Keys (PKS) 2020-05-29 12:35:30 +00:00
Stanislav Shwartsman
b69f2b052a extract calculation of MSR_IA32_XSS supported bits to a function 2020-01-03 19:33:16 +00:00
Stanislav Shwartsman
ff167d0f65 change a bit more defines to const with type 2019-12-26 16:48:33 +00:00
Stanislav Shwartsman
f90e5f4f44 Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071 
Only missing items (to be added soon):
  - Supervisor Shadow Stack EPT Control is not implemented yet
  - SMM placing for SSP
Currently have to be added manually to some CPUID model, for example to ICL-U
To enable configure with --enable-cet
 2019-12-20 07:42:07 +00:00
Stanislav Shwartsman
9b556d7656 fixed compilation error in crregs.cc xsave method init code - more methods to fix 2019-12-19 19:14:37 +00:00
Stanislav Shwartsman
258679b6dc fixed compilation error in crregs.cc xsave method init code 2019-12-19 19:12:39 +00:00
Stanislav Shwartsman
6b1992783e w/a compilation issue in gcc7 2019-12-18 18:19:52 +00:00
Stanislav Shwartsman
895c4b75df rewritten xsave/xrestore implementation in generic way to simplify adding new xsave/xrestore extensions 2019-12-16 16:14:51 +00:00
Stanislav Shwartsman
0c75e0beaf extract xcr0_support bits calculation to a function 2019-12-06 09:23:28 +00:00
Stanislav Shwartsman
773f1b7e42 cleanup return value of all instruction handlers 2018-02-16 07:57:32 +00:00
Stanislav Shwartsman
27a7925810 fix for MOV to CR3 in long mode with PCID enabled - patch by Kent Williams 2017-12-25 19:49:45 +00:00
Stanislav Shwartsman
e1532260e4 fixe compilation on cpu model missing cr4 2016-05-02 17:33:06 +00:00
Stanislav Shwartsman
ca5882b310 fixed compilation with cpu-level < 5 2016-04-21 15:39:49 +00:00
Stanislav Shwartsman
adc143684b implemented Intel architecture extensions published in recently published SDM 058: 
! Implemented UMIP: User Mode Instruction Prevention (don't allow execution of SLDT/SIDT/SGDT/STR/SMSW with CPL>0)
! Implemented RDPID instruction

Bugfixes in RDPKRU/WRPKRU instructions implementation (Protection Keys feature)
 2016-04-15 11:35:32 +00:00
Stanislav Shwartsman
e4832af5ab clean pkeys when not enabled to avoid side-effects 2016-03-19 21:15:56 +00:00
Stanislav Shwartsman
5b481fe34d correctly set up pkeys when enabling through cr4 2016-03-19 19:48:38 +00:00
Stanislav Shwartsman
cbe50a9539 enable PKE bit in CR4 2016-03-16 19:44:24 +00:00
Stanislav Shwartsman
8fe26816dc recalculate protection keys if cr0.wp change 2016-03-04 11:59:32 +00:00
Stanislav Shwartsman
b468316250 re-style old resolve macros after resolve function inlining 2015-05-16 21:06:59 +00:00
Stanislav Shwartsman
9f18573740 Rename BX_CPU_CALL_METHODR to BX_CPU_RESOLVE_ADDR and introduce special cases BX_CPU_RESOLVE_ADDR_64 (for 64-bit mode only) and BX_CPU_RESOLVE_ADDR_32 (for 32-bit mode only) 2015-05-11 19:23:09 +00:00
Stanislav Shwartsman
29efae3be3 adjust (c) in several files 2014-08-31 20:05:25 +00:00
Stanislav Shwartsman
5eb781e45f cleanup after cpu features interface rework 2014-08-31 19:22:41 +00:00
Stanislav Shwartsman
a85a9081b7 use shorter opcode names in the debug prints (skip the BX_IA_ prefix) 2013-12-02 20:06:59 +00:00
Stanislav Shwartsman
2b83146ae2 more avx-512 instructions implemented 2013-12-01 19:39:18 +00:00
Stanislav Shwartsman
ac82b38736 fixed typos causing compilation err 2013-11-30 18:39:22 +00:00
Stanislav Shwartsman
d082c6a0f9 implemented avx-512 masked load instructions 2013-11-30 18:37:25 +00:00