soda 2047c95e49 Decrease MIPS3_TLB_WIRED_ENTRIES from 8 to 2, ... and rename it to MIPS3_TLB_WIRED_UPAGES. The value of wired register becomes variable on arc port, and arc is the only mips3 port which uses the wired TLB entries 2..7.		2000-06-09 06:06:57 +00:00
..
ansi.h
aout_machdep.h
asm.h
bsd-aout.h
bswap.h
cachectl.h
cdefs.h
cpu.h	savefpregs() and loadfpregs() are defined in mips_machdep.c	2000-05-30 02:05:36 +00:00
cpuregs.h	Decrease MIPS3_TLB_WIRED_ENTRIES from 8 to 2,	2000-06-09 06:06:57 +00:00
db_machdep.h
ecoff_machdep.h
elf_machdep.h
endian_machdep.h
endian.h
float.h
ieee.h
ieeefp.h
kcore.h
kdbparam.h
limits.h
lock.h
locore.h	Rename RM5200 cache ops to mips3_*_2way in anticipation of using them	2000-06-06 17:41:07 +00:00
Makefile
math.h
mips1_pte.h	rename	2000-06-09 05:51:42 +00:00
mips3_pte.h	rename	2000-06-09 05:51:42 +00:00
mips_opcode.h
mips_param.h	make paddr_t 64bit on arc port by introducing _MIPS_PADDR_T_64BIT.	2000-06-09 04:36:43 +00:00
pcb.h
pmap.h
proc.h
profile.h	Fix kernel profiling so that it actually works:	2000-05-25 03:07:10 +00:00
psl.h
pte.h	rename	2000-06-09 05:51:42 +00:00
ptrace.h
r3900regs.h	MachForceCacheUpdate and cacheflush_bug have never been used in NetBSD,	2000-05-23 04:21:39 +00:00
reg.h
regdef.h
regnum.h
reloc.h
rnd.h	this header don't have to include <machine/locore.h>,	2000-06-09 04:24:22 +00:00
setjmp.h
signal.h
stdarg.h
sysarch.h
trap.h
types.h	make paddr_t 64bit on arc port by introducing _MIPS_PADDR_T_64BIT.	2000-06-09 04:36:43 +00:00
varargs.h
vmparam.h	USRIOSIZE had to be changed from 32 to 128,	2000-06-09 04:18:19 +00:00