Aren/NetBSD
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
113,390 Commits 606 Branches 0 Tags 3.1 GiB
ff0f991625
Commit Graph

1452 Commits

Author SHA1 Message Date
simonb
b2e8253950 Zero out the TX buffer when padding packet to ETHER_MIN_LEN-ETHER_CRC_LEN. 2003-01-17 12:40:20 +00:00
simonb
c018fbe68d Tidy up event counter increments a little. 2003-01-16 01:14:17 +00:00
simonb
c69f520bc8 Removed unused register map; this info is now passed in with the attach 
args.
 2003-01-16 01:05:39 +00:00
rafal
0cc0813590 Add the MIPS3_CONFIG_SE (name taken from Rm52xx manual) bit, which is the 
external cache enable bit -- this allows software to enable or disable the
(external) L2 cache on the R5k and Rm527x and the (external) L3 cache on
the Rm7k.  If the (external) cache is disabled, treat it as if there were
no cache for the purposes of the cache setup code.

Also, update sgimips code to use the new name.
 2003-01-10 03:22:48 +00:00
wiz
1035faff1d writable, not writeable. 2003-01-06 20:30:28 +00:00
thorpej
dbb0f0ebed Use aprint_normal() for cfprint routines. 2003-01-01 01:47:30 +00:00
manu
4a06119a9d Pass the system call table to trace_enter() and ktrsys() so that it is 
possible to use alternate system call tables. This is usefull for
displaying correctly the arguments in Mach binaries traces.

If NULL is given, then the regular systam call table for the process is used.
 2002-12-21 16:23:56 +00:00
simonb
5b6caeca74 Mark the Au1x00 CPUs as having a fully coherent data cache that doesn't 
require flushing (even in the instruction cache handlers).  This gives
about a 4% improvement in a "make depend" benchmark.

Mark the SB-1 CPUs as having a fully coherent data cache that only
require flushing in the instruction cache handlers.  This gives about
a 5% improvement in a "make depend" benchmark.
 2002-12-17 12:07:50 +00:00
simonb
2c1a832f25 Add support for caches where the data cache is fully coherent, and 
either requires flushing either only when the I cache ops are used
or not at all.  Currently only used by MIPS32/MIPS64 cache code.
 2002-12-17 12:04:29 +00:00
thorpej
e8cc3884de Rename __LDPGSZ to AOUT_LDPGSZ, to accurately reflect what it is. 2002-12-10 17:14:02 +00:00
thorpej
78ea2dd367 Use __LDPGSZ (which must be == USRTEXT) as the text address for a.out 
executables, and eliminate the USRTEXT constant, which was only used
by the a.out exec code.
 2002-12-10 05:14:24 +00:00
simonb
6a5e492b57 Remove the explicit `makeoptions MACHINE_ARCH="mipse{b,l}"' for kernel 
builds and use the endianness of the toolchain being used to determine
the endianness of the kernel.
 2002-12-09 22:54:09 +00:00
simonb
699bf96665 Drop the _KERNEL test; these functions are needed for SMP and other ports 
don't bother with a _KERNEL check.
 2002-12-05 02:56:51 +00:00
tsutsui
d03ac2a783 Fix botch in previous. This is pcb.h, not reg.h. 2002-11-30 22:50:01 +00:00
jdolecek
9a87c0933c make LKM friedlier - only include opt_* ifdef _KERNEL_OPT 2002-11-30 10:52:16 +00:00
simonb
fdd1e3b715 Standardise on #ifdef _MIPS_<header>_H_ for multiple inclusion tests. 2002-11-30 01:52:31 +00:00
simonb
d644dd9c43 Add multiple-inclusion protection. 2002-11-30 01:49:18 +00:00
lukem
0635de35a3 Remove KDIR=, since SYS_INCLUDE=symlinks and KDIR are not supported any more. 2002-11-26 23:30:07 +00:00
simonb
12c35ee2d2 New generic way-aware MIPS32/64 range-index cache functions with proper 
handling for phyiscally-indexed caches where the way size is greater than
the page size.
These work fine with pass 1 SB1 cores, so g/c those workarounds.

Much thanks to Chris Demetriou for many suggestions and helping me get
my head around all this.
 2002-11-24 07:41:29 +00:00
simonb
3a72aadc2b Add the VI bit in config 0. 2002-11-24 07:28:42 +00:00
simonb
3682edd3d4 Move the curpcb and segbase extern decls to cpu.h to better group together 
what will need to change for SMP.
Hide 'struct cpu_info' and some macros in #ifdef _KERNEL/#endif.
 2002-11-24 07:26:04 +00:00
cgd
8935916d0a initial support for mac features in new chip revs 2002-11-19 01:44:04 +00:00
simonb
5e3d4a224c Add cache_r4k_op_8lines_{16,32} macros to perform cache ops on 8 
consecutive lines.
 2002-11-17 06:40:43 +00:00
simonb
aa5595f691 Fix typo in the address of the Au1500 MAC1 enable register; 2nd MAC works 
on the Au1500 cpu now.
 2002-11-17 04:57:34 +00:00
simonb
ba1c8ffa9d Remove reference to mips_int5_evcnt from here; that is port-specific, 
not arch-specific.
 2002-11-17 04:56:57 +00:00
manu
d584ed9598 Add a realcode argument to trace_enter and ktrsyscall. realcode is the 
original system call number, which can be negative for a Mach trap.
We cannot just replace code by realcode, because ktrsyscall uses it as
an index in the system call table, thus crashing the kernel when the
value is negative.
 2002-11-15 20:06:00 +00:00
simonb
5bdb1a36ce Add a hack to mipsNN_pdcache_wbinv_range_index_32_4way() so that we 
use the index ops at a offset of the page size as well, controlled by
an MIPS64_SB1 check.  The SB1 D-cache way size is physically indexed
and twice as big as the page size (4k), so we weren't flushing all the
addresses we needed too.

XXX: This is kinda gross; will be cleaned up and made more generic soon.
There are still other SB1-specific issues to be cleaned up too...
 2002-11-15 01:23:17 +00:00
simonb
181d7f08c9 Use COP0_HAZARD_FPUENABLE instead of a hard-coded 4 NOPs when enabling 
the FPU.
 2002-11-15 01:16:18 +00:00
simonb
2aabe4d4e2 Define COP0_HAZARD_FPUENABLE as four nops. 
Include <mips/sb1regs.h> if MIPS64_SB1 is defined.
 2002-11-15 01:15:11 +00:00
simonb
383afcb5b6 Declare some CP0 hazards for the SB1 core. 2002-11-15 01:09:20 +00:00
simonb
28a1083dd2 Put the MIPS64_SB1 option in opt_cputype.h. 2002-11-15 01:02:49 +00:00
simonb
3d416825dc White space nits. 2002-11-15 00:58:32 +00:00
nisimura
abad61e77f Remove o32 stack layout exposure form cpu_fork(). 
Tested on R4000 and R3000.
 2002-11-12 14:00:41 +00:00
simonb
96c9d84cda Add support for the ST M41T81 RTC found on pass 2 swarm boards. 
XXX: Much of this should live in arch/sbmips instead of arch/mips/sibyte.
XXX: These should be replaced with MI SMBus drivers one day.
 2002-11-12 01:22:25 +00:00
he
aba5de5e41 Remove a PARANOIADIAG check which is a bit too paranoid. This one 
would now trigger whenever a previously used "cached" uarea was reused.

Reviewed by thorpej and chs.
 2002-11-11 22:30:15 +00:00
simonb
396f36cc12 Fix a typo in the on-board device selection machinery (which I thought 
I'd committed long ago).
 2002-11-11 16:39:18 +00:00
simonb
2e98091daf Make sure we use index ops (instead of hit ops) in the range index 
functions.
Fix typos in the cache_r4k_op_32_4way_load_off macro.

Both problems reported by Chris Demetriou.
 2002-11-10 11:11:39 +00:00
simonb
b8eff8f9aa Adapt for the ioctl ERESTART/EPASSTHROUGH changes. 
Make sure we don't tsleep() at splhigh/splserial.
 2002-11-10 11:06:11 +00:00
simonb
6fb837941b Remove some copyright notices that don't apply to this code. 2002-11-10 11:01:15 +00:00
nisimura
983202f1ed Change pmap_kenter_pa/pmap_kremove pair back to pmap_enter/pmap_remove 
in fear of the case choosen kva results in occupying inconsistent
distinctive cache lines of uva.
 2002-11-10 05:29:18 +00:00
nisimura
2a312dd17f Use pmap_enter_pa and pmap_kremove for vmapbuf/vunmapbuf, respectively. 
Have variable names renamed for the logic clarity.
 2002-11-10 02:27:50 +00:00
thorpej
84ccc9c46e Build with kernel with -msoft-float. 2002-11-09 20:34:26 +00:00
thorpej
ff114c4a59 Fix signed/unsigned comparison warnings. 2002-11-09 20:06:07 +00:00
thorpej
21ca5cbcc7 Make md_ss_addr a vaddr_t. 2002-11-09 20:05:57 +00:00
thorpej
800f626770 Fix signed/unsigned comparison warnings. 2002-11-09 20:00:20 +00:00
thorpej
0c2979d1c8 Fix signed/unsigned comparison warnings. 2002-11-09 19:35:52 +00:00
thorpej
4d7f6969a5 Make cache size/mask variables unsigned. 2002-11-09 19:34:39 +00:00
thorpej
73f78d5e61 Fix signed/unsigned comparison warnings. 2002-11-09 18:52:20 +00:00
thorpej
3689b18f89 * Add -mno-abicalls to AFLAGS. 
* GCC 3.3's traditional preprocessor functions properly now, so we
  no longer need to special-case it.
 2002-11-09 18:18:22 +00:00
thorpej
a99bec6b60 Nuke the CROSSDIR stuff. 2002-11-09 18:12:09 +00:00
nisimura
94df053502 Nuke "mips_reg_t" exposures from here. "mips_reg_t" will be 
corrected-back with "register_t" by completing the implementations
of N32 and LP64 environment.
 2002-11-09 10:59:52 +00:00
thorpej
e935239e3c No need to pass -mno-half-pic; NetBSD's compiler does not generate 
half-pic references.
 2002-11-09 07:31:08 +00:00
simonb
31fcce3c41 Include <sys/device.h> so this compiles again. 2002-11-09 04:13:03 +00:00
nisimura
8d6e18f90d - Make monolistic files into smaller manageable pieces, resulting 
three new files;
    sig_machdep.c (from mips_machdep.c)
    copy.S and sigcode.S (from locore.S)
- Nuke the local use of struct sigframe, which is now identical to
struct sigcontext, from sendsig() as the consequence of new signal
trampoline.
 2002-11-09 02:02:31 +00:00
cgd
48164df6b2 handle different SOC types and features a little better 2002-11-08 19:53:29 +00:00
cgd
f4a3e5f997 fix long-standing pasto in DMA config1 register address setting 2002-11-08 19:40:05 +00:00
cgd
49c87f0804 update to latest CFE API code 2002-11-08 19:35:38 +00:00
cgd
99a582aab5 Calculate end virtual address for cache ops before chopping low bits 
(line mask) off of starting address.  Otherwise, could miss the final
line that the ops should have been operating on.  Reviewed by simonb.
 2002-11-08 07:35:20 +00:00
cgd
1f2efd0d77 update SiByte includes from their master versions. (main differences: 
bug fixes, conditionalization of different chip support, new features.)
(Reviewed and tested by simonb.)
 2002-11-08 07:32:40 +00:00
simonb
0b3b87b6c8 Whitespace nit. 2002-11-08 04:13:13 +00:00
simonb
28cb103184 Note a new MIPS64_SB1 option that should be included in opt_cputype.h 
one day.
 2002-11-08 00:50:49 +00:00
simonb
220b08b128 Sprinkle a little more COP0_SYNC (in an unused function...). 2002-11-08 00:49:32 +00:00
cgd
a13b227af2 fix errors in calculating the ending VA to use in r4k_icache_sync_range_16 
and r5k_icache_sync_range_32.  (reviewed by thorpej.)
 2002-11-07 23:03:21 +00:00
cgd
d6cd994028 don't under COP0_SYNC. (approved by simonb.) 2002-11-07 05:39:48 +00:00
thorpej
0bc2a57e26 Use named indices for RA, SR, MULLO, MULHI, and EPC in the 
trapframe.
 2002-11-04 20:02:09 +00:00
thorpej
fab408c3af Use named indices for trapframe slots, and use the TA0-TA3 names 
where appropriate.
 2002-11-04 19:51:05 +00:00
thorpej
c8fbf16072 Define named constants for the trapframe register idices (they 
are different from the normal register numbers).  Use these names
in genassym.cf.  (Wow, how ever did that test kernel boot before...)
 2002-11-04 19:40:04 +00:00
thorpej
ad825a97f1 t4-t7 -> ta0-ta3 2002-11-04 18:54:13 +00:00
thorpej
1d0b5f8106 A few more t4-t7 -> ta0-ta3 that I missed before. 2002-11-04 18:45:55 +00:00
thorpej
731fe805a1 t4-t7 -> ta0-ta3 2002-11-04 18:41:37 +00:00
thorpej
32d1740afc Add FRAME_[TA0-TA3] and TF_REG_[TA0-TA3]. Change TF_REG_* to use 
defined constants for register indices, rather than hard-coded numbers.
 2002-11-04 18:41:03 +00:00
thorpej
65fdfe7d64 Add TA0-TA3 register indices. 2002-11-04 04:24:48 +00:00
thorpej
abaff8e1c6 t4-t7 -> ta0-ta3 2002-11-04 04:06:51 +00:00
thorpej
3e54f426e0 Rearrange mips_pagecopy() and mips_pagezero() for N32/LP64. 
XXX Does not yet use the correct reg names for new-ABI.
 2002-11-04 04:04:32 +00:00
thorpej
1bf923d5f3 Add N32 register vars. 2002-11-04 03:46:18 +00:00
thorpej
aa2b9a65fc Add SGI-compatible ta0-ta3 register names. These allow one to write 
asm code which can be built easily in old-ABI and new-ABI environemnts.

In old-ABI, they map to t4-t7, and in new-ABI, they map to a4-a7.  This
means that t0-t3,ta0-ta3,t8,t9 are available in both ABIs.

Because ta0-ta3 overlap with arg regs (albeit arg slots which are usually
unused), they should be used only if t0-t3,t8,t9 isn't enough.
 2002-11-04 03:38:32 +00:00
thorpej
bae541911c Add N32/N64 reg names. 2002-11-04 03:30:32 +00:00
thorpej
15d3b348c9 Add LP64 limits. 2002-11-03 20:02:39 +00:00
thorpej
9f9d6d33f4 Add LP64 types, limits, formats. 2002-11-03 19:55:23 +00:00
thorpej
f8dceffac5 Add LP64 macros. 2002-11-03 19:24:55 +00:00
thorpej
c88320f8d7 Add LP64 types. 2002-11-03 19:22:00 +00:00
thorpej
16084f1873 Add _LP64 types. 2002-11-03 17:43:07 +00:00
thorpej
c5adb2880e In the _MIPS_PADDR_T_64BIT case, only use "unsigned long long" if _LP64 
is not defined.
 2002-11-03 17:35:32 +00:00
nisimura
ad5b782866 Retire __HAVE_MD_RUNQUEUE from MD types.h and remove 
setrunqueue/remrunqueue from locore.S.  C codes are
compiled a bit shorter and provide better DIAGNOSTICs.
 2002-11-03 13:47:34 +00:00
nisimura
5a63303fc1 Add two PRiD values. 
- 0x55 for NEC Vr5500.  ISA might be MIPS64.
- 0x38 for Toshiba TX79.  This has thirty-two 128bit GPRs while
maintaining 32bit only virtual address space.  Any of pointer related
registers have 32bit.
 2002-11-03 13:16:11 +00:00
thorpej
3d93c95dc8 Make register_t == long long for N32, and == long for everthing else. 
Use register_t in label_t.
 2002-11-02 02:45:22 +00:00
thorpej
3517ae5f6a Define N32/N64 register usage. 2002-11-02 02:00:17 +00:00
jdolecek
e0cc03a09b merge kqueue branch into -current 
kqueue provides a stateful and efficient event notification framework
currently supported events include socket, file, directory, fifo,
pipe, tty and device changes, and monitoring of processes and signals

kqueue is supported by all writable filesystems in NetBSD tree
(with exception of Coda) and all device drivers supporting poll(2)

based on work done by Jonathan Lemon for FreeBSD
initial NetBSD port done by Luke Mewburn and Jason Thorpe
 2002-10-23 09:10:23 +00:00
chs
b79663cf62 eliminate PT_ENTRY_NULL in favor of plain old NULL. 2002-10-14 05:11:21 +00:00
simonb
b1a30609f9 Install the kernel linker script in /usr/lkm/ldscript so that modload(8) 
works without needing to resort to -A abuse.  LKMs work cleanly on MIPS
now.
 2002-10-10 01:59:29 +00:00
chs
993948e989 count executable image pages as executable for vm-usage purposes. 
also, always do the VTEXT vs. v_writecount mutual exclusion
(which we previously skipped if the text or data segment was empty).
 2002-10-05 22:34:02 +00:00
thorpej
89bf5a8f8e Add trailing ; to CFATTACH_DECL. 2002-10-02 15:52:22 +00:00
thorpej
c5e91d447d Use CFATTACH_DECL(). 2002-10-02 04:55:47 +00:00
thorpej
c4cbfcf060 Use CFATTACH_DECL(). 2002-10-01 02:54:11 +00:00
thorpej
f818766afe Declare all cfattach structures const. 2002-09-27 20:31:45 +00:00
provos
0f09ed48a5 remove trailing \n in panic(). approved perry. 2002-09-27 15:35:29 +00:00
thorpej
6c88de3b53 Introduce a new routine, config_match(), which invokes the 
cfattach->ca_match function in behalf of the caller.  Use it
rather than invoking cfattach->ca_match directly.
 2002-09-27 03:17:40 +00:00
thorpej
d1ad2ac4f2 Rather than referencing the cfdriver directly in the cfdata entries, 
instead use a string naming the driver.  The cfdriver is then looked
up in a list which is built at run-time.
 2002-09-27 02:24:06 +00:00
thorpej
274c086b22 Remove <sys/map.h> 2002-09-26 18:54:30 +00:00
simonb
63096043b3 Use "#define\t" instead of "#define ". 2002-09-22 08:30:56 +00:00