simonb 5bdb1a36ce Add a hack to mipsNN_pdcache_wbinv_range_index_32_4way() so that we ... use the index ops at a offset of the page size as well, controlled by an MIPS64_SB1 check. The SB1 D-cache way size is physically indexed and twice as big as the page size (4k), so we weren't flushing all the addresses we needed too. XXX: This is kinda gross; will be cleaned up and made more generic soon. There are still other SB1-specific issues to be cleaned up too...		2002-11-15 01:23:17 +00:00
..
alchemy	Fix a typo in the on-board device selection machinery (which I thought	2002-11-11 16:39:18 +00:00
bonito	Update to rev 1.48 from Algorithmics; adds BONITO64 register definitions.	2002-08-18 16:00:33 +00:00
cfe	update to latest CFE API code	2002-11-08 19:35:38 +00:00
conf	Put the MIPS64_SB1 option in opt_cputype.h.	2002-11-15 01:02:49 +00:00
include	Define COP0_HAZARD_FPUENABLE as four nops.	2002-11-15 01:15:11 +00:00
mips	Add a hack to mipsNN_pdcache_wbinv_range_index_32_4way() so that we	2002-11-15 01:23:17 +00:00
sibyte	Add support for the ST M41T81 RTC found on pass 2 swarm boards.	2002-11-12 01:22:25 +00:00
Makefile	Install the kernel linker script in /usr/lkm/ldscript so that modload(8)	2002-10-10 01:59:29 +00:00
Makefile.inc