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update SiByte includes from their master versions. (main differences: 

bug fixes, conditionalization of different chip support, new features.)
(Reviewed and tested by simonb.)
This commit is contained in:
cgd 2002-11-08 07:32:40 +00:00
parent 6f485abe93
commit 1f2efd0d77
13 changed files with 705 additions and 130 deletions
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123
sys/arch/mips/sibyte/include/sb1250_defs.h
View File

@ -48,6 +48,122 @@
* THE POSSIBILITY OF SUCH DAMAGE.
********************************************************************* */
#ifndef _SB1250_DEFS_H
#define _SB1250_DEFS_H
/*
* These headers require ANSI C89 string concatenation, and GCC or other
* 'long long' (64-bit integer) support.
*/
#if !defined(__STDC__) && !defined(_MSC_VER)
#error SiByte headers require ANSI C89 support
#endif
/* *********************************************************************
* Macros for feature tests, used to enable include file features
* for chip features only present in certain chip revisions.
*
* SIBYTE_HDR_FEATURES may be defined to be the mask value chip/revision
* which is to be exposed by the headers. If undefined, it defaults to
* "all features."
*
* Use like:
*
* #define SIBYTE_HDR_FEATURES SIBYTE_HDR_FMASK_112x_PASS1
*
* Generate defines only for that revision of chip.
*
* #if SIBYTE_HDR_FEATURE(chip,pass)
*
* True if header features for that revision or later of
* that particular chip type are enabled in SIBYTE_HDR_FEATURES.
* (Use this to bracket #defines for features present in a given
* revision and later.)
*
* Note that there is no implied ordering between chip types.
*
* Note also that 'chip' and 'pass' must textually exactly
* match the defines below. So, for example,
* SIBYTE_HDR_FEATURE(112x, PASS1) is OK, but
* SIBYTE_HDR_FEATURE(1120, pass1) is not (for two reasons).
*
* #if SIBYTE_HDR_FEATURE_UP_TO(chip,pass)
*
* Same as SIBYTE_HDR_FEATURE, but true for the named revision
* and earlier revisions of the named chip type.
*
* #if SIBYTE_HDR_FEATURE_EXACT(chip,pass)
*
* Same as SIBYTE_HDR_FEATURE, but only true for the named
* revision of the named chip type. (Note that this CANNOT
* be used to verify that you're compiling only for that
* particular chip/revision. It will be true any time this
* chip/revision is included in SIBYTE_HDR_FEATURES.)
*
* #if SIBYTE_HDR_FEATURE_CHIP(chip)
*
* True if header features for (any revision of) that chip type
* are enabled in SIBYTE_HDR_FEATURES. (Use this to bracket
* #defines for features specific to a given chip type.)
*
* Mask values currently include room for additional revisions of each
* chip type, but can be renumbered at will. Note that they MUST fit
* into 31 bits and may not include C type constructs, for safe use in
* CPP conditionals. Bit positions within chip types DO indicate
* ordering, so be careful when adding support for new minor revs.
********************************************************************* */
#define SIBYTE_HDR_FMASK_1250_ALL 0x00000ff
#define SIBYTE_HDR_FMASK_1250_PASS1 0x0000001
#define SIBYTE_HDR_FMASK_1250_PASS2 0x0000002
#define SIBYTE_HDR_FMASK_112x_ALL 0x0000f00
#define SIBYTE_HDR_FMASK_112x_PASS1 0x0000100
#define SIBYTE_HDR_FMASK_112x_PASS3 0x0000200
/* Bit mask for chip/revision. (use _ALL for all revisions of a chip). */
#define SIBYTE_HDR_FMASK(chip, pass) \
(SIBYTE_HDR_FMASK_ ## chip ## _ ## pass)
#define SIBYTE_HDR_FMASK_ALLREVS(chip) \
(SIBYTE_HDR_FMASK_ ## chip ## _ALL)
#define SIBYTE_HDR_FMASK_ALL \
(SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL)
#ifndef SIBYTE_HDR_FEATURES
#define SIBYTE_HDR_FEATURES SIBYTE_HDR_FMASK_ALL
#endif
/* Bit mask for revisions of chip exclusively before the named revision. */
#define SIBYTE_HDR_FMASK_BEFORE(chip, pass) \
((SIBYTE_HDR_FMASK(chip, pass) - 1) & SIBYTE_HDR_FMASK_ALLREVS(chip))
/* Bit mask for revisions of chip exclusively after the named revision. */
#define SIBYTE_HDR_FMASK_AFTER(chip, pass) \
(~(SIBYTE_HDR_FMASK(chip, pass) \
| (SIBYTE_HDR_FMASK(chip, pass) - 1)) & SIBYTE_HDR_FMASK_ALLREVS(chip))
/* True if header features enabled for (any revision of) that chip type. */
#define SIBYTE_HDR_FEATURE_CHIP(chip) \
(!! (SIBYTE_HDR_FMASK_ALLREVS(chip) & SIBYTE_HDR_FEATURES))
/* True if header features enabled for that rev or later, inclusive. */
#define SIBYTE_HDR_FEATURE(chip, pass) \
(!! ((SIBYTE_HDR_FMASK(chip, pass) \
| SIBYTE_HDR_FMASK_AFTER(chip, pass)) & SIBYTE_HDR_FEATURES))
/* True if header features enabled for exactly that rev. */
#define SIBYTE_HDR_FEATURE_EXACT(chip, pass) \
(!! (SIBYTE_HDR_FMASK(chip, pass) & SIBYTE_HDR_FEATURES))
/* True if header features enabled for that rev or before, inclusive. */
#define SIBYTE_HDR_FEATURE_UP_TO(chip, pass) \
(!! ((SIBYTE_HDR_FMASK(chip, pass) \
| SIBYTE_HDR_FMASK_BEFORE(chip, pass)) & SIBYTE_HDR_FEATURES))
/* *********************************************************************
* Naming schemes for constants in these files:
@ -89,9 +205,6 @@
#ifndef _SB1250_DEFS_H
#define _SB1250_DEFS_H
/*
* Cast to 64-bit number. Presumably the syntax is different in
* assembly language.
@ -139,8 +252,8 @@
#if !defined(__ASSEMBLER__)
#define SBWRITECSR(csr,val) *((volatile uint64_t *) MIPS_PHYS_TO_KSEG1(csr)) = (val)
#define SBREADCSR(csr) (*((volatile uint64_t *) MIPS_PHYS_TO_KSEG1(csr)))
#define SBWRITECSR(csr,val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val)
#define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr)))
#endif /* __ASSEMBLER__ */
#endif

194
sys/arch/mips/sibyte/include/sb1250_dma.h
View File

@ -70,8 +70,23 @@
#define M_DMA_DROP _SB_MAKEMASK1(0)
#define M_DMA_CHAIN_SEL _SB_MAKEMASK1(1)
#define M_DMA_RESERVED1 _SB_MAKEMASK1(2)
#define S_DMA_DESC_TYPE _SB_MAKE64(1)
#define M_DMA_DESC_TYPE _SB_MAKE64(2,S_DMA_DESC_TYPE)
#define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x,S_DMA_DESC_TYPE)
#define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x,S_DMA_DESC_TYPE,M_DMA_DESC_TYPE)
#define K_DMA_DESC_TYPE_RING_AL 0
#define K_DMA_DESC_TYPE_CHAIN_AL 1
#if SIBYTE_HDR_FEATURE(112x, PASS3)
#define K_DMA_DESC_TYPE_RING_UAL_WI 2
#define K_DMA_DESC_TYPE_RING_UAL_RMW 3
#endif
#define M_DMA_EOP_INT_EN _SB_MAKEMASK1(3)
#define M_DMA_HWM_INT_EN _SB_MAKEMASK1(4)
#define M_DMA_LWM_INT_EN _SB_MAKEMASK1(5)
@ -99,7 +114,7 @@
#define G_DMA_LOW_WATERMARK(x) _SB_GETVALUE(x,S_DMA_LOW_WATERMARK,M_DMA_LOW_WATERMARK)
/*
* Ethernet and Serial DMA Configuration Register 2 (Table 7-5)
* Ethernet and Serial DMA Configuration Register 1 (Table 7-5)
* Registers: DMA_CONFIG1_MAC_x_RX_CH_0
* Registers: DMA_CONFIG1_DMA_x_TX_CH_0
* Registers: DMA_CONFIG1_SER_x_RX
@ -113,6 +128,12 @@
#define M_DMA_NO_DSCR_UPDT _SB_MAKEMASK1(4)
#define M_DMA_L2CA _SB_MAKEMASK1(5)
#if SIBYTE_HDR_FEATURE(112x, PASS3)
#define M_DMA_RX_XTRA_STATUS _SB_MAKEMASK1(6)
#define M_DMA_TX_CPU_PAUSE _SB_MAKEMASK1(6)
#define M_DMA_TX_FC_PAUSE_EN _SB_MAKEMASK1(7)
#endif
#define M_DMA_MBZ1 _SB_MAKEMASK(6,15)
#define S_DMA_HDR_SIZE _SB_MAKE64(21)
@ -158,9 +179,26 @@
#define S_DMA_CURDSCR_ADDR _SB_MAKE64(0)
#define M_DMA_CURDSCR_ADDR _SB_MAKEMASK(40,S_DMA_CURDSCR_ADDR)
#define S_DMA_CURDSCR_COUNT _SB_MAKE64(48)
#define S_DMA_CURDSCR_COUNT _SB_MAKE64(40)
#define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT)
#if SIBYTE_HDR_FEATURE(112x, PASS3)
#define M_DMA_TX_CH_PAUSE_ON _SB_MAKEMASK1(56)
#endif
/*
* Receive Packet Drop Registers
*/
#if SIBYTE_HDR_FEATURE(112x, PASS3)
#define S_DMA_OODLOST_RX _SB_MAKE64(0)
#define M_DMA_OODLOST_RX _SB_MAKEMASK(16,S_DMA_OODLOST_RX)
#define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x,S_DMA_OODLOST_RX,M_DMA_OODLOST_RX)
#define S_DMA_EOP_COUNT_RX _SB_MAKE64(16)
#define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8,S_DMA_EOP_COUNT_RX)
#define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x,S_DMA_EOP_COUNT_RX,M_DMA_EOP_COUNT_RX)
#endif
/* *********************************************************************
* DMA Descriptors
********************************************************************* */
@ -171,6 +209,8 @@
#define S_DMA_DSCRA_OFFSET _SB_MAKE64(0)
#define M_DMA_DSCRA_OFFSET _SB_MAKEMASK(5,S_DMA_DSCRA_OFFSET)
#define V_DMA_DSCRA_OFFSET(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_OFFSET)
#define G_DMA_DSCRA_OFFSET(x) _SB_GETVALUE(x,S_DMA_DSCRA_OFFSET,M_DMA_DSCRA_OFFSET)
/* Note: Don't shift the address over, just mask it with the mask below */
#define S_DMA_DSCRA_A_ADDR _SB_MAKE64(5)
@ -178,11 +218,22 @@
#define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR)
#if SIBYTE_HDR_FEATURE(112x, PASS3)
#define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0)
#define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40,S_DMA_DSCRA_A_ADDR_UA)
#endif
#define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40)
#define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE)
#define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE)
#define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE)
#if SIBYTE_HDR_FEATURE(112x, PASS3)
#define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40)
#define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8,S_DMA_DSCRA_DSCR_CNT)
#define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x,S_DMA_DSCRA_DSCR_CNT,M_DMA_DSCRA_DSCR_CNT)
#endif
#define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49)
#define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50)
@ -201,6 +252,13 @@
#define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS)
#define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS)
#if SIBYTE_HDR_FEATURE(112x, PASS3)
#define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8)
#define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_A_SIZE)
#define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_A_SIZE)
#define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_A_SIZE,M_DMA_DSCRB_A_SIZE)
#endif
#define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10)
/* Note: Don't shift the address over, just mask it with the mask below */
@ -214,11 +272,26 @@
#define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49)
#if SIBYTE_HDR_FEATURE(112x, PASS3)
#define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48)
#define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2,S_DMA_DSCRB_PKT_SIZE_MSB)
#define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB)
#define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB,M_DMA_DSCRB_PKT_SIZE_MSB)
#endif
#define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50)
#define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE)
#define V_DMA_DSCRB_PKT_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE)
#define G_DMA_DSCRB_PKT_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE,M_DMA_DSCRB_PKT_SIZE)
/*
* from pass2 some bits in dscr_b are also used for rx status
*/
#define S_DMA_DSCRB_STATUS _SB_MAKE64(0)
#define M_DMA_DSCRB_STATUS _SB_MAKEMASK(1,S_DMA_DSCRB_STATUS)
#define V_DMA_DSCRB_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_STATUS)
#define G_DMA_DSCRB_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRB_STATUS,M_DMA_DSCRB_STATUS)
/*
* Ethernet Descriptor Status Bits (Table 7-15)
*/
@ -226,8 +299,15 @@
#define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51)
#define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52)
/* Note: BADTCPCS is actually in DSCR_A */
#define M_DMA_ETHRX_BADTCPCS _SB_MAKEMASK1(0) /* PASS2 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
/* Note: BADTCPCS is actually in DSCR_B options field */
#define M_DMA_ETHRX_BADTCPCS _SB_MAKEMASK1(0)
#endif /* 1250 PASS2 || 112x PASS1 */
#if SIBYTE_HDR_FEATURE(112x, PASS3)
#define M_DMA_ETH_VLAN_FLAG _SB_MAKEMASK1(1)
#define M_DMA_ETH_CRC_FLAG _SB_MAKEMASK1(2)
#endif
#define S_DMA_ETHRX_RXCH 53
#define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH)
@ -248,8 +328,8 @@
#define K_DMA_ETHRX_PKTTYPE_USER2 6
#define K_DMA_ETHRX_PKTTYPE_USER3 7
#define M_DMA_ETHRX_MATCH_EXACT _SB_MAKEMASK1(58)
#define M_DMA_ETHRX_MATCH_HASH _SB_MAKEMASK1(59)
#define M_DMA_ETHRX_MATCH_HASH _SB_MAKEMASK1(58)
#define M_DMA_ETHRX_MATCH_EXACT _SB_MAKEMASK1(59)
#define M_DMA_ETHRX_BCAST _SB_MAKEMASK1(60)
#define M_DMA_ETHRX_MCAST _SB_MAKEMASK1(61)
#define M_DMA_ETHRX_BAD _SB_MAKEMASK1(62)
@ -374,6 +454,83 @@
#define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT,\
M_DM_CUR_DSCR_DSCR_COUNT)
#if SIBYTE_HDR_FEATURE(112x, PASS1)
/*
* Data Mover Channel Partial Result Registers
* Register: DM_PARTIAL_0
* Register: DM_PARTIAL_1
* Register: DM_PARTIAL_2
* Register: DM_PARTIAL_3
*/
#define S_DM_PARTIAL_CRC_PARTIAL _SB_MAKE64(0)
#define M_DM_PARTIAL_CRC_PARTIAL _SB_MAKEMASK(32,S_DM_PARTIAL_CRC_PARTIAL)
#define V_DM_PARTIAL_CRC_PARTIAL(r) _SB_MAKEVALUE(r,S_DM_PARTIAL_CRC_PARTIAL)
#define G_DM_PARTIAL_CRC_PARTIAL(r) _SB_GETVALUE(r,S_DM_PARTIAL_CRC_PARTIAL,\
M_DM_PARTIAL_CRC_PARTIAL)
#define S_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKE64(32)
#define M_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKEMASK(16,S_DM_PARTIAL_TCPCS_PARTIAL)
#define V_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_MAKEVALUE(r,S_DM_PARTIAL_TCPCS_PARTIAL)
#define G_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_GETVALUE(r,S_DM_PARTIAL_TCPCS_PARTIAL,\
M_DM_PARTIAL_TCPCS_PARTIAL)
#define M_DM_PARTIAL_ODD_BYTE _SB_MAKEMASK1(48)
#endif /* 112x PASS1 */
#if SIBYTE_HDR_FEATURE(112x, PASS1)
/*
* Data Mover CRC Definition Registers
* Register: CRC_DEF_0
* Register: CRC_DEF_1
*/
#define S_CRC_DEF_CRC_INIT _SB_MAKE64(0)
#define M_CRC_DEF_CRC_INIT _SB_MAKEMASK(32,S_CRC_DEF_CRC_INIT)
#define V_CRC_DEF_CRC_INIT(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_INIT)
#define G_CRC_DEF_CRC_INIT(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_INIT,\
M_CRC_DEF_CRC_INIT)
#define S_CRC_DEF_CRC_POLY _SB_MAKE64(32)
#define M_CRC_DEF_CRC_POLY _SB_MAKEMASK(32,S_CRC_DEF_CRC_POLY)
#define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_POLY)
#define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_POLY,\
M_CRC_DEF_CRC_POLY)
#endif /* 112x PASS1 */
#if SIBYTE_HDR_FEATURE(112x, PASS1)
/*
* Data Mover CRC/Checksum Definition Registers
* Register: CTCP_DEF_0
* Register: CTCP_DEF_1
*/
#define S_CTCP_DEF_CRC_TXOR _SB_MAKE64(0)
#define M_CTCP_DEF_CRC_TXOR _SB_MAKEMASK(32,S_CTCP_DEF_CRC_TXOR)
#define V_CTCP_DEF_CRC_TXOR(r) _SB_MAKEVALUE(r,S_CTCP_DEF_CRC_TXOR)
#define G_CTCP_DEF_CRC_TXOR(r) _SB_GETVALUE(r,S_CTCP_DEF_CRC_TXOR,\
M_CTCP_DEF_CRC_TXOR)
#define S_CTCP_DEF_TCPCS_INIT _SB_MAKE64(32)
#define M_CTCP_DEF_TCPCS_INIT _SB_MAKEMASK(16,S_CTCP_DEF_TCPCS_INIT)
#define V_CTCP_DEF_TCPCS_INIT(r) _SB_MAKEVALUE(r,S_CTCP_DEF_TCPCS_INIT)
#define G_CTCP_DEF_TCPCS_INIT(r) _SB_GETVALUE(r,S_CTCP_DEF_TCPCS_INIT,\
M_CTCP_DEF_TCPCS_INIT)
#define S_CTCP_DEF_CRC_WIDTH _SB_MAKE64(48)
#define M_CTCP_DEF_CRC_WIDTH _SB_MAKEMASK(2,S_CTCP_DEF_CRC_WIDTH)
#define V_CTCP_DEF_CRC_WIDTH(r) _SB_MAKEVALUE(r,S_CTCP_DEF_CRC_WIDTH)
#define G_CTCP_DEF_CRC_WIDTH(r) _SB_GETVALUE(r,S_CTCP_DEF_CRC_WIDTH,\
M_CTCP_DEF_CRC_WIDTH)
#define K_CTCP_DEF_CRC_WIDTH_4 0
#define K_CTCP_DEF_CRC_WIDTH_2 1
#define K_CTCP_DEF_CRC_WIDTH_1 2
#define M_CTCP_DEF_CRC_BIT_ORDER _SB_MAKEMASK1(50)
#endif /* 112x PASS1 */
/*
* Data Mover Descriptor Doubleword "A" (Table 7-26)
*/
@ -384,10 +541,9 @@
#define M_DM_DSCRA_UN_DEST _SB_MAKEMASK1(40)
#define M_DM_DSCRA_UN_SRC _SB_MAKEMASK1(41)
#define M_DM_DSCRA_INTERRUPT _SB_MAKEMASK1(42)
/*#define M_DM_DSCRA_THROTTLE _SB_MAKEMASK1(43) */ /* REMOVED PASS2 */
#define M_DM_DSCRA_RD_BKOFF _SB_MAKEMASK1(52) /* PASS2 */
#define M_DM_DSCRA_WR_BKOFF _SB_MAKEMASK1(53) /* PASS2 */
#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
#define M_DM_DSCRA_THROTTLE _SB_MAKEMASK1(43)
#endif /* up to 1250 PASS1 */
#define S_DM_DSCRA_DIR_DEST _SB_MAKE64(44)
#define M_DM_DSCRA_DIR_DEST _SB_MAKEMASK(2,S_DM_DSCRA_DIR_DEST)
@ -421,7 +577,23 @@
#define M_DM_DSCRA_L2C_DEST _SB_MAKEMASK1(50)
#define M_DM_DSCRA_L2C_SRC _SB_MAKEMASK1(51)
#define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(10,54)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_DM_DSCRA_RD_BKOFF _SB_MAKEMASK1(52)
#define M_DM_DSCRA_WR_BKOFF _SB_MAKEMASK1(53)
#endif /* 1250 PASS2 || 112x PASS1 */
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_DM_DSCRA_TCPCS_EN _SB_MAKEMASK1(54)
#define M_DM_DSCRA_TCPCS_RES _SB_MAKEMASK1(55)
#define M_DM_DSCRA_TCPCS_AP _SB_MAKEMASK1(56)
#define M_DM_DSCRA_CRC_EN _SB_MAKEMASK1(57)
#define M_DM_DSCRA_CRC_RES _SB_MAKEMASK1(58)
#define M_DM_DSCRA_CRC_AP _SB_MAKEMASK1(59)
#define M_DM_DSCRA_CRC_DFN _SB_MAKEMASK1(60)
#define M_DM_DSCRA_CRC_XBIT _SB_MAKEMASK1(61)
#endif /* 112x PASS1 */
#define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3,61)
/*
* Data Mover Descriptor Doubleword "B" (Table 7-25)

47
sys/arch/mips/sibyte/include/sb1250_genbus.h
View File

@ -58,22 +58,33 @@
* Generic Bus Region Configuration Registers (Table 11-4)
*/
#define M_IO_RDY_ACTIVE _SB_MAKEMASK1(0)
#define M_IO_ENA_RDY _SB_MAKEMASK1(1)
#define S_IO_RDY_ACTIVE 0
#define M_IO_RDY_ACTIVE _SB_MAKEMASK1(S_IO_RDY_ACTIVE)
#define S_IO_ENA_RDY 1
#define M_IO_ENA_RDY _SB_MAKEMASK1(S_IO_ENA_RDY)
#define S_IO_WIDTH_SEL 2
#define M_IO_WIDTH_SEL _SB_MAKEMASK(2,S_IO_WIDTH_SEL)
#define K_IO_WIDTH_SEL_1 0
#define K_IO_WIDTH_SEL_2 1
#define K_IO_WIDTH_SEL_1L 2 /* PASS2 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define K_IO_WIDTH_SEL_1L 2
#endif /* 1250 PASS2 || 112x PASS1 */
#define K_IO_WIDTH_SEL_4 3
#define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x,S_IO_WIDTH_SEL)
#define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x,S_IO_WIDTH_SEL,M_IO_WIDTH_SEL)
#define M_IO_PARITY_ENA _SB_MAKEMASK1(4)
#define M_IO_BURST_EN _SB_MAKEMASK1(5) /* PASS2 */
#define M_IO_PARITY_ODD _SB_MAKEMASK1(6)
#define M_IO_NONMUX _SB_MAKEMASK1(7)
#define S_IO_PARITY_ENA 4
#define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define S_IO_BURST_EN 5
#define M_IO_BURST_EN _SB_MAKEMASK1(S_IO_BURST_EN)
#endif /* 1250 PASS2 || 112x PASS1 */
#define S_IO_PARITY_ODD 6
#define M_IO_PARITY_ODD _SB_MAKEMASK1(S_IO_PARITY_ODD)
#define S_IO_NONMUX 7
#define M_IO_NONMUX _SB_MAKEMASK1(S_IO_NONMUX)
#define S_IO_TIMEOUT 8
#define M_IO_TIMEOUT _SB_MAKEMASK(8,S_IO_TIMEOUT)
@ -111,17 +122,21 @@
#define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_ALE_WIDTH)
#define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x,S_IO_ALE_WIDTH,M_IO_ALE_WIDTH)
#define M_IO_EARLY_CS _SB_MAKEMASK1(3) /* PASS2 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_IO_EARLY_CS _SB_MAKEMASK1(3)
#endif /* 1250 PASS2 || 112x PASS1 */
#define S_IO_ALE_TO_CS 4
#define M_IO_ALE_TO_CS _SB_MAKEMASK(2,S_IO_ALE_TO_CS)
#define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_CS)
#define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x,S_IO_ALE_TO_CS,M_IO_ALE_TO_CS)
#define S_IO_BURST_WIDTH _SB_MAKE64(6) /* PASS2 */
#define M_IO_BURST_WIDTH _SB_MAKEMASK(2,S_IO_BURST_WIDTH) /* PASS2 */
#define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x,S_IO_BURST_WIDTH) /* PASS2 */
#define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x,S_IO_BURST_WIDTH,M_IO_BURST_WIDTH) /* PASS2 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define S_IO_BURST_WIDTH _SB_MAKE64(6)
#define M_IO_BURST_WIDTH _SB_MAKEMASK(2,S_IO_BURST_WIDTH)
#define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x,S_IO_BURST_WIDTH)
#define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x,S_IO_BURST_WIDTH,M_IO_BURST_WIDTH)
#endif /* 1250 PASS2 || 112x PASS1 */
#define S_IO_CS_WIDTH 8
#define M_IO_CS_WIDTH _SB_MAKEMASK(5,S_IO_CS_WIDTH)
@ -143,7 +158,9 @@
#define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_WRITE)
#define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x,S_IO_ALE_TO_WRITE,M_IO_ALE_TO_WRITE)
#define M_IO_RDY_SYNC _SB_MAKEMASK1(3) /* PASS2 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_IO_RDY_SYNC _SB_MAKEMASK1(3)
#endif /* 1250 PASS2 || 112x PASS1 */
#define S_IO_WRITE_WIDTH 4
#define M_IO_WRITE_WIDTH _SB_MAKEMASK(4,S_IO_WRITE_WIDTH)
@ -183,7 +200,9 @@
#define M_IO_TIMEOUT_INT _SB_MAKEMASK1(10)
#define M_IO_ILL_ADDR_INT _SB_MAKEMASK1(11)
#define M_IO_MULT_CS_INT _SB_MAKEMASK1(12)
#define M_IO_COH_ERR _SB_MAKEMASK1(14) /* PASS2 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_IO_COH_ERR _SB_MAKEMASK1(14)
#endif /* 1250 PASS2 || 112x PASS1 */
/*
* PCMCIA configuration register (Table 12-6)

28
sys/arch/mips/sibyte/include/sb1250_int.h
View File

@ -94,8 +94,10 @@
#define K_INT_MBOX_1 27
#define K_INT_MBOX_2 28
#define K_INT_MBOX_3 29
#define K_INT_CYCLE_CP0_INT 30 /* PASS2 */
#define K_INT_CYCLE_CP1_INT 31 /* PASS2 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define K_INT_CYCLE_CP0_INT 30
#define K_INT_CYCLE_CP1_INT 31
#endif /* 1250 PASS2 || 112x PASS1 */
#define K_INT_GPIO_0 32
#define K_INT_GPIO_1 33
#define K_INT_GPIO_2 34
@ -125,9 +127,11 @@
#define K_INT_PCI_INTC 58
#define K_INT_PCI_INTD 59
#define K_INT_SPARE_2 60
#define K_INT_MAC_0_CH1 61 /* PASS2 */
#define K_INT_MAC_1_CH1 62 /* PASS2 */
#define K_INT_MAC_2_CH1 63 /* PASS2 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define K_INT_MAC_0_CH1 61
#define K_INT_MAC_1_CH1 62
#define K_INT_MAC_2_CH1 63
#endif /* 1250 PASS2 || 112x PASS1 */
/*
* Mask values for each interrupt
@ -163,8 +167,10 @@
#define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1)
#define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2)
#define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3)
#define M_INT_CYCLE_CP0_INT _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT) /* PASS2 */
#define M_INT_CYCLE_CP1_INT _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT) /* PASS2 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_INT_CYCLE_CP0_INT _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT)
#define M_INT_CYCLE_CP1_INT _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT)
#endif /* 1250 PASS2 || 112x PASS1 */
#define M_INT_GPIO_0 _SB_MAKEMASK1(K_INT_GPIO_0)
#define M_INT_GPIO_1 _SB_MAKEMASK1(K_INT_GPIO_1)
#define M_INT_GPIO_2 _SB_MAKEMASK1(K_INT_GPIO_2)
@ -194,9 +200,11 @@
#define M_INT_PCI_INTC _SB_MAKEMASK1(K_INT_PCI_INTC)
#define M_INT_PCI_INTD _SB_MAKEMASK1(K_INT_PCI_INTD)
#define M_INT_SPARE_2 _SB_MAKEMASK1(K_INT_SPARE_2)
#define M_INT_MAC_0_CH1 _SB_MAKEMASK1(K_INT_MAC_0_CH1) /* PASS2 */
#define M_INT_MAC_1_CH1 _SB_MAKEMASK1(K_INT_MAC_1_CH1) /* PASS2 */
#define M_INT_MAC_2_CH1 _SB_MAKEMASK1(K_INT_MAC_2_CH1) /* PASS2 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_INT_MAC_0_CH1 _SB_MAKEMASK1(K_INT_MAC_0_CH1)
#define M_INT_MAC_1_CH1 _SB_MAKEMASK1(K_INT_MAC_1_CH1)
#define M_INT_MAC_2_CH1 _SB_MAKEMASK1(K_INT_MAC_2_CH1)
#endif /* 1250 PASS2 || 112x PASS1 */
/*
* Interrupt mappings

23
sys/arch/mips/sibyte/include/sb1250_l2c.h
View File

@ -119,4 +119,27 @@
#define L2C_ENTRIES_PER_WAY 4096
#define L2C_NUM_WAYS 4
#if SIBYTE_HDR_FEATURE(112x, PASS1)
/*
* L2 Read Misc. register (A_L2_READ_MISC)
*/
#define S_L2C_MISC_NO_WAY 10
#define M_L2C_MISC_NO_WAY _SB_MAKEMASK(4,S_L2C_MISC_NO_WAY)
#define V_L2C_MISC_NO_WAY(x) _SB_MAKEVALUE(x,S_L2C_MISC_NO_WAY)
#define G_L2C_MISC_NO_WAY(x) _SB_GETVALUE(x,S_L2C_MISC_NO_WAY,M_L2C_MISC_NO_WAY)
#define M_L2C_MISC_ECC_CLEANUP_DIS _SB_MAKEMASK1(9)
#define M_L2C_MISC_MC_PRIO_LOW _SB_MAKEMASK1(8)
#define M_L2C_MISC_SOFT_DISABLE_T _SB_MAKEMASK1(7)
#define M_L2C_MISC_SOFT_DISABLE_B _SB_MAKEMASK1(6)
#define M_L2C_MISC_SOFT_DISABLE_R _SB_MAKEMASK1(5)
#define M_L2C_MISC_SOFT_DISABLE_L _SB_MAKEMASK1(4)
#define M_L2C_MISC_SCACHE_DISABLE_T _SB_MAKEMASK1(3)
#define M_L2C_MISC_SCACHE_DISABLE_B _SB_MAKEMASK1(2)
#define M_L2C_MISC_SCACHE_DISABLE_R _SB_MAKEMASK1(1)
#define M_L2C_MISC_SCACHE_DISABLE_L _SB_MAKEMASK1(0)
#endif /* 112x PASS1 */
#endif

22
sys/arch/mips/sibyte/include/sb1250_ldt.h
View File

@ -87,7 +87,9 @@
#define R_LDT_TYPE1_SRIRXNUM 0x0058
#define R_LDT_TYPE1_ERRSTATUS 0x0068
#define R_LDT_TYPE1_SRICTRL 0x006C
#define R_LDT_TYPE1_ADDSTATUS 0x0070 /* PASS2 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define R_LDT_TYPE1_ADDSTATUS 0x0070
#endif /* 1250 PASS2 || 112x PASS1 */
#define R_LDT_TYPE1_TXBUFCNT 0x00C8
#define R_LDT_TYPE1_EXPCRC 0x00DC
#define R_LDT_TYPE1_RXCRC 0x00F0
@ -177,7 +179,9 @@
* register (Table 8-15), offset 0x1C
*/
#define M_LDT_STATUS_VGAEN _SB_MAKEMASK1_32(3) /* PASS2 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_LDT_STATUS_VGAEN _SB_MAKEMASK1_32(3)
#endif /* 1250 PASS2 || 112x PASS1 */
#define M_LDT_STATUS_CAPLIST _SB_MAKEMASK1_32(20)
#define M_LDT_STATUS_66MHZCAP _SB_MAKEMASK1_32(21)
#define M_LDT_STATUS_RESERVED2 _SB_MAKEMASK1_32(22)
@ -298,9 +302,13 @@
#define M_LDT_SRICMD_SIPREADY _SB_MAKEMASK1_32(16)
#define M_LDT_SRICMD_SYNCPTRCTL _SB_MAKEMASK1_32(17)
#define M_LDT_SRICMD_REDUCESYNCZERO _SB_MAKEMASK1_32(18)
/*#define M_LDT_SRICMD_DISSTARVATIONCNT _SB_MAKEMASK1_32(19) */ /* PASS1 */
#define M_LDT_SRICMD_DISMULTTXVLD _SB_MAKEMASK1_32(19) /* PASS2 */
#define M_LDT_SRICMD_EXPENDIAN _SB_MAKEMASK1_32(26) /* PASS2 */
#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
#define M_LDT_SRICMD_DISSTARVATIONCNT _SB_MAKEMASK1_32(19) /* PASS1 */
#endif /* up to 1250 PASS1 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_LDT_SRICMD_DISMULTTXVLD _SB_MAKEMASK1_32(19)
#define M_LDT_SRICMD_EXPENDIAN _SB_MAKEMASK1_32(26)
#endif /* 1250 PASS2 || 112x PASS1 */
#define S_LDT_SRICMD_RXMARGIN 20
@ -419,14 +427,16 @@
#define V_LDT_TXBUFCNT_RDATA(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_RDATA)
#define G_LDT_TXBUFCNT_RDATA(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_RDATA,M_LDT_TXBUFCNT_RDATA)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
/*
* Additional Status Register (PASS2)
* Additional Status Register
*/
#define S_LDT_ADDSTATUS_TGTDONE 0
#define M_LDT_ADDSTATUS_TGTDONE _SB_MAKEMASK_32(8,S_LDT_ADDSTATUS_TGTDONE)
#define V_LDT_ADDSTATUS_TGTDONE(x) _SB_MAKEVALUE_32(x,S_LDT_ADDSTATUS_TGTDONE)
#define G_LDT_ADDSTATUS_TGTDONE(x) _SB_GETVALUE_32(x,S_LDT_ADDSTATUS_TGTDONE,M_LDT_ADDSTATUS_TGTDONE)
#endif /* 1250 PASS2 || 112x PASS1 */
#endif

125
sys/arch/mips/sibyte/include/sb1250_mac.h
View File

@ -145,7 +145,13 @@
#define M_MAC_BYPASS_16 _SB_MAKEMASK1(42)
#define M_MAC_BYPASS_FCS_CHK _SB_MAKEMASK1(43)
#define M_MAC_RX_CH_SEL_MSB _SB_MAKEMASK1(44) /* PASS2 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_MAC_RX_CH_SEL_MSB _SB_MAKEMASK1(44)
#endif /* 1250 PASS2 || 112x PASS1 */
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_MAC_SPLIT_CH_SEL _SB_MAKEMASK1(45)
#endif /* 112x PASS1 */
#define S_MAC_BYPASS_IFG _SB_MAKE64(46)
#define M_MAC_BYPASS_IFG _SB_MAKEMASK(8,S_MAC_BYPASS_IFG)
@ -217,14 +223,24 @@
*/
#define S_MAC_TX_WR_THRSH _SB_MAKE64(0)
/* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6,S_MAC_TX_WR_THRSH) */ /* PASS1 */
#define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7,S_MAC_TX_WR_THRSH) /* PASS2 */
#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
/* XXX: Can't enable, as it has the same name as a pass2+ define below. */
/* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6,S_MAC_TX_WR_THRSH) */
#endif /* up to 1250 PASS1 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7,S_MAC_TX_WR_THRSH)
#endif /* 1250 PASS2 || 112x PASS1 */
#define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_WR_THRSH)
#define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_WR_THRSH,M_MAC_TX_WR_THRSH)
#define S_MAC_TX_RD_THRSH _SB_MAKE64(8)
/* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6,S_MAC_TX_RD_THRSH) */ /* PASS1 */
#define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7,S_MAC_TX_RD_THRSH) /* PASS2 */
#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
/* XXX: Can't enable, as it has the same name as a pass2+ define below. */
/* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6,S_MAC_TX_RD_THRSH) */
#endif /* up to 1250 PASS1 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7,S_MAC_TX_RD_THRSH)
#endif /* 1250 PASS2 || 112x PASS1 */
#define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RD_THRSH)
#define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RD_THRSH,M_MAC_TX_RD_THRSH)
@ -248,10 +264,12 @@
#define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RL_THRSH)
#define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RL_THRSH,M_MAC_RX_RL_THRSH)
#define S_MAC_ENC_FC_THRSH _SB_MAKE64(56) /* PASS2 */
#define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6,S_MAC_ENC_FC_THRSH) /* PASS2 */
#define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x,S_MAC_ENC_FC_THRSH) /* PASS2 */
#define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x,S_MAC_ENC_FC_THRSH,M_MAC_ENC_FC_THRSH) /* PASS2 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define S_MAC_ENC_FC_THRSH _SB_MAKE64(56)
#define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6,S_MAC_ENC_FC_THRSH)
#define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x,S_MAC_ENC_FC_THRSH)
#define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x,S_MAC_ENC_FC_THRSH,M_MAC_ENC_FC_THRSH)
#endif /* 1250 PASS2 || 112x PASS1 */
/*
* MAC Frame Configuration Registers (Table 9-15)
@ -260,11 +278,19 @@
* Register: MAC_FRAME_CFG_2
*/
/* XXXCGD: ??? Unused in pass2? */
#define S_MAC_IFG_RX _SB_MAKE64(0)
#define M_MAC_IFG_RX _SB_MAKEMASK(6,S_MAC_IFG_RX)
#define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x,S_MAC_IFG_RX)
#define G_MAC_IFG_RX(x) _SB_GETVALUE(x,S_MAC_IFG_RX,M_MAC_IFG_RX)
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#define S_MAC_PRE_LEN _SB_MAKE64(0)
#define M_MAC_PRE_LEN _SB_MAKEMASK(6,S_MAC_PRE_LEN)
#define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x,S_MAC_PRE_LEN)
#define G_MAC_PRE_LEN(x) _SB_GETVALUE(x,S_MAC_PRE_LEN,M_MAC_PRE_LEN)
#endif /* 112x PASS1 */
#define S_MAC_IFG_TX _SB_MAKE64(6)
#define M_MAC_IFG_TX _SB_MAKEMASK(6,S_MAC_IFG_TX)
#define V_MAC_IFG_TX(x) _SB_MAKEVALUE(x,S_MAC_IFG_TX)
@ -337,10 +363,12 @@
#define V_MAC_SLOT_SIZE_100 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_100)
#define V_MAC_SLOT_SIZE_1000 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_1000)
#define K_MAC_MIN_FRAMESZ_FIFO _SB_MAKE64(9)
#define K_MAC_MIN_FRAMESZ_DEFAULT _SB_MAKE64(64)
#define K_MAC_MAX_FRAMESZ_DEFAULT _SB_MAKE64(1518)
#define K_MAC_MAX_FRAMESZ_JUMBO _SB_MAKE64(9216)
#define V_MAC_MIN_FRAMESZ_FIFO V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_FIFO)
#define V_MAC_MIN_FRAMESZ_DEFAULT V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_DEFAULT)
#define V_MAC_MAX_FRAMESZ_DEFAULT V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_DEFAULT)
#define V_MAC_MAX_FRAMESZ_JUMBO V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_JUMBO)
@ -352,7 +380,24 @@
* Register: MAC_VLANTAG_2
*/
/* No bit fields: lower 32 bits of register are the tags */
#define S_MAC_VLAN_TAG _SB_MAKE64(0)
#define M_MAC_VLAN_TAG _SB_MAKEMASK(32,S_MAC_VLAN_TAG)
#define V_MAC_VLAN_TAG(x) _SB_MAKEVALUE(x,S_MAC_VLAN_TAG)
#define G_MAC_VLAN_TAG(x) _SB_GETVALUE(x,S_MAC_VLAN_TAG,M_MAC_VLAN_TAG)
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#define S_MAC_TX_PKT_OFFSET _SB_MAKE64(32)
#define M_MAC_TX_PKT_OFFSET _SB_MAKEMASK(8,S_MAC_TX_PKT_OFFSET)
#define V_MAC_TX_PKT_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_TX_PKT_OFFSET)
#define G_MAC_TX_PKT_OFFSET(x) _SB_GETVALUE(x,S_MAC_TX_PKT_OFFSET,M_MAC_TX_PKT_OFFSET)
#define S_MAC_TX_CRC_OFFSET _SB_MAKE64(40)
#define M_MAC_TX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_TX_CRC_OFFSET)
#define V_MAC_TX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_TX_CRC_OFFSET)
#define G_MAC_TX_CRC_OFFSET(x) _SB_GETVALUE(x,S_MAC_TX_CRC_OFFSET,M_MAC_TX_CRC_OFFSET)
#define M_MAC_CH_BASE_FC_EN _SB_MAKEMASK1(48)
#endif /* 112x PASS1 */
/*
* MAC Status Registers (Table 9-17)
@ -393,6 +438,25 @@
#define M_MAC_INT_DSCR _SB_MAKEMASK1(5)
#define M_MAC_INT_ERR _SB_MAKEMASK1(6)
#define M_MAC_INT_DZERO _SB_MAKEMASK1(7) /* only for TX channels */
#define M_MAC_INT_DROP _SB_MAKEMASK1(7) /* only for RX channels */
/*
* In the following definitions we use ch (0/1) and txrx (TX=1, RX=0, see
* also DMA_TX/DMA_RX in sb_regs.h).
*/
#define S_MAC_STATUS_CH_OFFSET(ch,txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH)
#define M_MAC_STATUS_CHANNEL(ch,txrx) _SB_MAKEVALUE(_SB_MAKEMASK(8,0),S_MAC_STATUS_CH_OFFSET(ch,txrx))
#define M_MAC_STATUS_EOP_COUNT(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT,S_MAC_STATUS_CH_OFFSET(ch,txrx))
#define M_MAC_STATUS_EOP_TIMER(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER,S_MAC_STATUS_CH_OFFSET(ch,txrx))
#define M_MAC_STATUS_EOP_SEEN(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN,S_MAC_STATUS_CH_OFFSET(ch,txrx))
#define M_MAC_STATUS_HWM(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_HWM,S_MAC_STATUS_CH_OFFSET(ch,txrx))
#define M_MAC_STATUS_LWM(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_LWM,S_MAC_STATUS_CH_OFFSET(ch,txrx))
#define M_MAC_STATUS_DSCR(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DSCR,S_MAC_STATUS_CH_OFFSET(ch,txrx))
#define M_MAC_STATUS_ERR(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_ERR,S_MAC_STATUS_CH_OFFSET(ch,txrx))
#define M_MAC_STATUS_DZERO(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DZERO,S_MAC_STATUS_CH_OFFSET(ch,txrx))
#define M_MAC_STATUS_DROP(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DROP,S_MAC_STATUS_CH_OFFSET(ch,txrx))
#define M_MAC_STATUS_OTHER_ERR _SB_MAKEVALUE(_SB_MAKEMASK(7,0),40)
#define M_MAC_RX_UNDRFL _SB_MAKEMASK1(40)
@ -402,13 +466,19 @@
#define M_MAC_LTCOL_ERR _SB_MAKEMASK1(44)
#define M_MAC_EXCOL_ERR _SB_MAKEMASK1(45)
#define M_MAC_CNTR_OVRFL_ERR _SB_MAKEMASK1(46)
#define M_MAC_SPLIT_EN _SB_MAKEMASK1(47) /* interrupt mask only */ /* PASS2 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_MAC_SPLIT_EN _SB_MAKEMASK1(47) /* interrupt mask only */
#endif /* 1250 PASS2 || 112x PASS1 */
#define S_MAC_COUNTER_ADDR _SB_MAKE64(47)
#define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5,S_MAC_COUNTER_ADDR)
#define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x,S_MAC_COUNTER_ADDR)
#define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x,S_MAC_COUNTER_ADDR,M_MAC_COUNTER_ADDR)
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_MAC_TX_PAUSE_ON _SB_MAKEMASK1(52)
#endif /* 112x PASS1 */
/*
* MAC Fifo Pointer Registers (Table 9-19) [Debug register]
* Register: MAC_FIFO_PTRS_0
@ -462,6 +532,15 @@
/* No bitfields */
/*
* MAC Receive Address Filter Mask Registers
* Registers: MAC_ADDRMASK0_0 and MAC_ADDRMASK0_1
* Registers: MAC_ADDRMASK1_0 and MAC_ADDRMASK1_1
* Registers: MAC_ADDRMASK2_0 and MAC_ADDRMASK2_1
*/
/* No bitfields */
/*
* MAC Recieve Address Filter Hash Match Registers (Table 9-22)
* Registers: MAC_HASH0_0 through MAC_HASH7_0
@ -523,13 +602,35 @@
#define M_MAC_MCAST_INV _SB_MAKEMASK1(4)
#define M_MAC_BCAST_EN _SB_MAKEMASK1(5)
#define M_MAC_DIRECT_INV _SB_MAKEMASK1(6)
#define M_MAC_ALLMCAST_EN _SB_MAKEMASK1(7) /* PASS2 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_MAC_ALLMCAST_EN _SB_MAKEMASK1(7)
#endif /* 1250 PASS2 || 112x PASS1 */
#define S_MAC_IPHDR_OFFSET _SB_MAKE64(8)
#define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8,S_MAC_IPHDR_OFFSET)
#define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_IPHDR_OFFSET)
#define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x,S_MAC_IPHDR_OFFSET,M_MAC_IPHDR_OFFSET)
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16)
#define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_RX_CRC_OFFSET)
#define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_CRC_OFFSET)
#define G_MAC_RX_CRC_OFFSET(x) _SB_GETVALUE(x,S_MAC_RX_CRC_OFFSET,M_MAC_RX_CRC_OFFSET)
#define S_MAC_RX_PKT_OFFSET _SB_MAKE64(24)
#define M_MAC_RX_PKT_OFFSET _SB_MAKEMASK(8,S_MAC_RX_PKT_OFFSET)
#define V_MAC_RX_PKT_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_PKT_OFFSET)
#define G_MAC_RX_PKT_OFFSET(x) _SB_GETVALUE(x,S_MAC_RX_PKT_OFFSET,M_MAC_RX_PKT_OFFSET)
#define M_MAC_FWDPAUSE_EN _SB_MAKEMASK1(32)
#define M_MAC_VLAN_DET_EN _SB_MAKEMASK1(33)
#define S_MAC_RX_CH_MSN_SEL _SB_MAKE64(34)
#define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8,S_MAC_RX_CH_MSN_SEL)
#define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_MSN_SEL)
#define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_MSN_SEL,M_MAC_RX_CH_MSN_SEL)
#endif /* 112x PASS1 */
/*
* MAC Receive Channel Select Registers (Table 9-25)
*/

8
sys/arch/mips/sibyte/include/sb1250_mc.h
View File

@ -208,6 +208,10 @@
#define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x,S_MC_ADDR_DRIVE,M_MC_ADDR_DRIVE)
#define V_MC_ADDR_DRIVE_DEFAULT V_MC_ADDR_DRIVE(0x0)
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_MC_REF_DISABLE _SB_MAKEMASK1(30)
#endif /* 112x PASS1 */
#define M_MC_DLL_BYPASS _SB_MAKEMASK1(31)
#define S_MC_DQI_SKEW 32
@ -308,6 +312,10 @@
#define M_MC_EXTERNALDECODE _SB_MAKEMASK1(35)
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_MC_PRE_ON_A8 _SB_MAKEMASK1(36)
#define M_MC_RAM_WITH_A13 _SB_MAKEMASK1(38)
#endif /* 112x PASS1 */

14
sys/arch/mips/sibyte/include/sb1250_pci.h
View File

@ -84,8 +84,10 @@
#define R_PCI_TYPE0_ERRORADDR 0x0084
#define R_PCI_TYPE0_ADDSTATUS 0x0088
#define R_PCI_TYPE0_SUBSYSSET 0x008C /* only accessible from ZBBus */
#define R_PCI_TYPE0_READHOST 0x0094 /* Read Host register */ /* PASS2 */
#define R_PCI_TYPE0_ADXTEND 0x0098 /* Adaptive Extend register */ /* PASS2 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define R_PCI_TYPE0_READHOST 0x0094 /* Read Host register */
#define R_PCI_TYPE0_ADXTEND 0x0098 /* Adaptive Extend register */
#endif /* 1250 PASS2 || 112x PASS1 */
/*
* PCI Device ID register
@ -264,14 +266,15 @@
#define M_PCI_ASTATUS_RETRYINTMASK _SB_MAKEMASK1_32(5)
#define M_PCI_ASTATUS_SIGNALINTA _SB_MAKEMASK1_32(6)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
/*
* Read Host Register (PASS2)
* Read Host Register
*/
#define M_PCI_READHOST_RDHOST _SB_MAKEMASK1_32(0) /* PASS2 */
#define M_PCI_READHOST_RDHOST _SB_MAKEMASK1_32(0)
/*
* Adaptive Extend Register (PASS2)
* Adaptive Extend Register
*/
#define S_PCI_ADXTEND_NOM_TAR_RETRY 1
@ -286,6 +289,7 @@
#define M_PCI_ADXTEND_DIS_DMAR_IOW_DEP _SB_MAKEMASK1_32(6)
#define M_PCI_ADXTEND_DIS_MEMRD_BE _SB_MAKEMASK1_32(6)
#endif /* 1250 PASS2 || 112x PASS1 */
#endif

101
sys/arch/mips/sibyte/include/sb1250_regs.h
View File

@ -74,6 +74,10 @@
* Memory Controller Registers
********************************************************************* */
/*
* XXX: can't remove MC base 0 if 112x, since it's used by other macros,
* since there is one reg there (but it could get its addr/offset constant).
*/
#define A_MC_BASE_0 0x0010051000
#define A_MC_BASE_1 0x0010052000
#define MC_REGISTER_SPACING 0x1000
@ -118,15 +122,25 @@
* L2 Cache Control Registers
********************************************************************* */
#define A_L2_READ_ADDRESS 0x0010040018
#define A_L2_EEC_ADDRESS 0x0010040038
#define A_L2_READ_TAG 0x0010040018
#define A_L2_ECC_TAG 0x0010040038
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#define A_L2_READ_MISC 0x0010040058
#endif /* 112x PASS1 */
#define A_L2_WAY_DISABLE 0x0010041000
#define A_L2_MAKEDISABLE(x) (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8))
#define A_L2_MGMT_TAG_BASE 0x00D0000000
#define A_L2_CACHE_DISABLE 0x0010042000 /* PASS2 */
#define A_L2_MAKECACHEDISABLE(x) (A_L2_CACHE_DISABLE | (((x)&0x0F) << 8)) /* PASS2 */
#define A_L2_MISC_CONFIG 0x0010043000 /* PASS2 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define A_L2_CACHE_DISABLE 0x0010042000
#define A_L2_MAKECACHEDISABLE(x) (A_L2_CACHE_DISABLE | (((x)&0x0F) << 8))
#define A_L2_MISC_CONFIG 0x0010043000
#endif /* 1250 PASS2 || 112x PASS1 */
/* Backward-compatibility definitions. */
/* XXX: discourage people from using these constants. */
#define A_L2_READ_ADDRESS A_L2_READ_TAG
#define A_L2_EEC_ADDRESS A_L2_ECC_TAG
/* *********************************************************************
@ -143,7 +157,9 @@
#define A_MAC_BASE_0 0x0010064000
#define A_MAC_BASE_1 0x0010065000
#if SIBYTE_HDR_FEATURE_CHIP(1250)
#define A_MAC_BASE_2 0x0010066000
#endif /* 1250 */
#define MAC_SPACING 0x1000
#define MAC_DMA_TXRX_SPACING 0x0400
@ -152,6 +168,7 @@
#define DMA_TX 1
#define MAC_NUM_DMACHAN 2 /* channels per direction */
/* XXX: not correct; depends on SOC type. */
#define MAC_NUM_PORTS 3
#define A_MAC_CHANNEL_BASE(macnum) \
@ -195,6 +212,9 @@
#define R_MAC_DMA_CUR_DSCRA 0x00000020
#define R_MAC_DMA_CUR_DSCRB 0x00000028
#define R_MAC_DMA_CUR_DSCRADDR 0x00000030
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#define R_MAC_DMA_OODPKTLOST_RX 0x00000038 /* rx only */
#endif /* 112x PASS1 */
/*
* RMON Counters
@ -233,6 +253,10 @@
#define R_MAC_ADFILTER_CFG 0x00000200
#define R_MAC_ETHERNET_ADDR 0x00000208
#define R_MAC_PKT_TYPE 0x00000210
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#define R_MAC_ADMASK0 0x00000218
#define R_MAC_ADMASK1 0x00000220
#endif /* 112x PASS1 */
#define R_MAC_HASH_BASE 0x00000240
#define R_MAC_ADDR_BASE 0x00000280
#define R_MAC_CHLO0_BASE 0x00000300
@ -242,7 +266,9 @@
#define R_MAC_INT_MASK 0x00000410
#define R_MAC_TXD_CTL 0x00000420
#define R_MAC_MDIO 0x00000428
#define R_MAC_STATUS1 0x00000430 /* PASS2 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define R_MAC_STATUS1 0x00000430
#endif /* 1250 PASS2 || 112x PASS1 */
#define R_MAC_DEBUG_STATUS 0x00000448
#define MAC_HASH_COUNT 8
@ -273,9 +299,11 @@
#define R_DUART_RX_HOLD 0x160
#define R_DUART_TX_HOLD 0x170
#define R_DUART_FULL_CTL 0x140 /* PASS2 */
#define R_DUART_OPCR_X 0x180 /* PASS2 */
#define R_DUART_AUXCTL_X 0x190 /* PASS2 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define R_DUART_FULL_CTL 0x140
#define R_DUART_OPCR_X 0x180
#define R_DUART_AUXCTL_X 0x190
#endif /* 1250 PASS2 || 112x PASS1 */
/*
@ -341,13 +369,15 @@
#define A_DUART_INPORT_CHNG_A 0x00100603D0
#define A_DUART_INPORT_CHNG_B 0x00100603E0
#define A_DUART_FULL_CTL_A 0x0010060140 /* PASS2 */
#define A_DUART_FULL_CTL_B 0x0010060240 /* PASS2 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define A_DUART_FULL_CTL_A 0x0010060140
#define A_DUART_FULL_CTL_B 0x0010060240
#define A_DUART_OPCR_A 0x0010060180 /* PASS2 */
#define A_DUART_OPCR_B 0x0010060280 /* PASS2 */
#define A_DUART_OPCR_A 0x0010060180
#define A_DUART_OPCR_B 0x0010060280
#define A_DUART_INPORT_CHNG_DEBUG 0x00100603F0 /* PASS2 */
#define A_DUART_INPORT_CHNG_DEBUG 0x00100603F0
#endif /* 1250 PASS2 || 112x PASS1 */
/* *********************************************************************
@ -484,6 +514,10 @@
#define A_IO_DRIVE_1 0x0010061308
#define A_IO_DRIVE_2 0x0010061310
#define A_IO_DRIVE_3 0x0010061318
#define A_IO_DRIVE_BASE A_IO_DRIVE_0
#define IO_DRIVE_REGISTER_SPACING 8
#define R_IO_DRIVE(x) ((x)*IO_DRIVE_REGISTER_SPACING)
#define A_IO_DRIVE(x) (A_IO_DRIVE_BASE + R_IO_DRIVE(x))
#define R_IO_INTERRUPT_STATUS 0x0A00
#define R_IO_INTERRUPT_DATA0 0x0A10
@ -615,11 +649,13 @@
#define A_SCD_TIMER_CNT_3 0x0010020188
#define A_SCD_TIMER_CFG_3 0x0010020198
#define A_SCD_SCRATCH 0x0010020C10 /* PASS2 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define A_SCD_SCRATCH 0x0010020C10
#define A_SCD_ZBBUS_CYCLE_COUNT 0x0010030000 /* PASS2 */
#define A_SCD_ZBBUS_CYCLE_CP0 0x0010020C00 /* PASS2 */
#define A_SCD_ZBBUS_CYCLE_CP1 0x0010020C08 /* PASS2 */
#define A_SCD_ZBBUS_CYCLE_COUNT 0x0010030000
#define A_SCD_ZBBUS_CYCLE_CP0 0x0010020C00
#define A_SCD_ZBBUS_CYCLE_CP1 0x0010020C08
#endif /* 1250 PASS2 || 112x PASS1 */
/* *********************************************************************
@ -647,7 +683,9 @@
#define A_ADDR_TRAP_CFG_1 0x0010020448
#define A_ADDR_TRAP_CFG_2 0x0010020450
#define A_ADDR_TRAP_CFG_3 0x0010020458
#define A_ADDR_TRAP_REG_DEBUG 0x0010020460 /* PASS2 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define A_ADDR_TRAP_REG_DEBUG 0x0010020460
#endif /* 1250 PASS2 || 112x PASS1 */
/* *********************************************************************
@ -657,6 +695,7 @@
#define A_IMR_CPU0_BASE 0x0010020000
#define A_IMR_CPU1_BASE 0x0010022000
#define IMR_REGISTER_SPACING 0x2000
#define IMR_REGISTER_SPACING_SHIFT 13
#define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING)
#define A_IMR_REGISTER(cpu,reg) (A_IMR_MAPPER(cpu)+(reg))
@ -693,7 +732,9 @@
********************************************************************* */
#define A_SCD_BUS_ERR_STATUS 0x0010020880
#define A_SCD_BUS_ERR_STATUS_DEBUG 0x00100208D0 /* PASS2 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define A_SCD_BUS_ERR_STATUS_DEBUG 0x00100208D0
#endif /* 1250 PASS2 || 112x PASS1 */
#define A_BUS_ERR_DATA_0 0x00100208A0
#define A_BUS_ERR_DATA_1 0x00100208A8
#define A_BUS_ERR_DATA_2 0x00100208B0
@ -748,6 +789,26 @@
#define R_DM_CUR_DSCR_ADDR 0x0000000010
#define R_DM_DSCR_BASE_DEBUG 0x0000000018
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#define A_DM_PARTIAL_0 0x0010020ba0
#define A_DM_PARTIAL_1 0x0010020ba8
#define A_DM_PARTIAL_2 0x0010020bb0
#define A_DM_PARTIAL_3 0x0010020bb8
#define DM_PARTIAL_REGISTER_SPACING 0x8
#define A_DM_PARTIAL(idx) (A_DM_PARTIAL_0 + ((idx) * DM_PARTIAL_REGISTER_SPACING))
#endif /* 112x PASS1 */
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#define A_DM_CRC_0 0x0010020b80
#define A_DM_CRC_1 0x0010020b90
#define DM_CRC_REGISTER_SPACING 0x10
#define DM_CRC_NUM_CHANNELS 2
#define A_DM_CRC_BASE(idx) (A_DM_CRC_0 + ((idx) * DM_CRC_REGISTER_SPACING))
#define A_DM_CRC_REGISTER(idx,reg) (A_DM_CRC_BASE(idx) + (reg))
#define R_CRC_DEF_0 0x00
#define R_CTCP_DEF_0 0x08
#endif /* 112x PASS1 */
/* *********************************************************************
* Physical Address Map

138
sys/arch/mips/sibyte/include/sb1250_scd.h
View File

@ -68,18 +68,72 @@
#define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION)
#define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION)
#define K_SYS_REVISION_PASS1 1
#define K_SYS_REVISION_PASS2 3
#define K_SYS_REVISION_PASS2_2 16
#define K_SYS_REVISION_PASS3 32
#if SIBYTE_HDR_FEATURE_CHIP(1250)
#define K_SYS_REVISION_BCM1250_PASS1 1
#define K_SYS_REVISION_BCM1250_PASS2 3
#define K_SYS_REVISION_BCM1250_PASS2_2 16
#define K_SYS_REVISION_BCM1250_PASS3 32
/* XXX: discourage people from using these constants. */
#define K_SYS_REVISION_PASS1 K_SYS_REVISION_BCM1250_PASS1
#define K_SYS_REVISION_PASS2 K_SYS_REVISION_BCM1250_PASS2
#define K_SYS_REVISION_PASS2_2 K_SYS_REVISION_BCM1250_PASS2_2
#define K_SYS_REVISION_PASS3 K_SYS_REVISION_BCM1250_PASS3
#endif /* 1250 */
#if SIBYTE_HDR_FEATURE_CHIP(112x)
#define K_SYS_REVISION_BCM112x_PASS1 32
#endif /* 112x */
/* XXX: discourage people from using these constants. */
#define S_SYS_PART _SB_MAKE64(16)
#define M_SYS_PART _SB_MAKEMASK(16,S_SYS_PART)
#define V_SYS_PART(x) _SB_MAKEVALUE(x,S_SYS_PART)
#define G_SYS_PART(x) _SB_GETVALUE(x,S_SYS_PART,M_SYS_PART)
/* XXX: discourage people from using these constants. */
#define K_SYS_PART_SB1250 0x1250
#define K_SYS_PART_SB1125 0x1125
#define K_SYS_PART_BCM1120 0x1121
#define K_SYS_PART_BCM1125 0x1123
#define K_SYS_PART_BCM1125H 0x1124
/* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */
#define S_SYS_SOC_TYPE _SB_MAKE64(16)
#define M_SYS_SOC_TYPE _SB_MAKEMASK(4,S_SYS_SOC_TYPE)
#define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x,S_SYS_SOC_TYPE)
#define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x,S_SYS_SOC_TYPE,M_SYS_SOC_TYPE)
#define K_SYS_SOC_TYPE_BCM1250 0x0
#define K_SYS_SOC_TYPE_BCM1120 0x1
#define K_SYS_SOC_TYPE_BCM1250_ALT 0x2 /* 1250pass2 w/ 1/4 L2. */
#define K_SYS_SOC_TYPE_BCM1125 0x3
#define K_SYS_SOC_TYPE_BCM1125H 0x4
#define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. */
/*
* Calculate correct SOC type given a copy of system revision register.
*
* (For the assembler version, sysrev and dest may be the same register.
* Also, it clobbers AT.)
*/
#ifdef __ASSEMBLER__
#define SYS_SOC_TYPE(dest, sysrev) \
.set push ; \
.set reorder ; \
dsrl dest, sysrev, S_SYS_SOC_TYPE ; \
andi dest, dest, (M_SYS_SOC_TYPE >> S_SYS_SOC_TYPE); \
beq dest, K_SYS_SOC_TYPE_BCM1250_ALT, 991f ; \
beq dest, K_SYS_SOC_TYPE_BCM1250_ALT2, 991f ; \
b 992f ; \
991: li dest, K_SYS_SOC_TYPE_BCM1250 ; \
992: \
.set pop
#else
#define SYS_SOC_TYPE(sysrev) \
((G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT \
|| G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT2) \
? K_SYS_SOC_TYPE_BCM1250 : G_SYS_SOC_TYPE(sysrev))
#endif
#define S_SYS_WID _SB_MAKE64(32)
#define M_SYS_WID _SB_MAKEMASK(32,S_SYS_WID)
@ -171,7 +225,9 @@
#define M_SYS_MISR_MODE _SB_MAKEMASK1(61)
#define M_SYS_MISR_RESET _SB_MAKEMASK1(62)
#define M_SYS_SW_FLAG _SB_MAKEMASK1(63) /* PASS2 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_SYS_SW_FLAG _SB_MAKEMASK1(63)
#endif /* 1250 PASS2 || 112x PASS1 */
/*
@ -265,48 +321,48 @@
#define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x,S_SCD_BERR_RID)
#define G_SCD_BERR_RID(x) _SB_GETVALUE(x,S_SCD_BERR_RID,M_SCD_BERR_RID)
#define S_SCD_BERR_DCODE 22
#define M_SCD_BERR_DCODE _SB_MAKEMASK(3,S_SCD_BERR_DCODE)
#define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x,S_SCD_BERR_DCODE)
#define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x,S_SCD_BERR_DCODE,M_SCD_BERR_DCODE)
#define S_SCD_BERR_DCODE 22
#define M_SCD_BERR_DCODE _SB_MAKEMASK(3,S_SCD_BERR_DCODE)
#define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x,S_SCD_BERR_DCODE)
#define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x,S_SCD_BERR_DCODE,M_SCD_BERR_DCODE)
#define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30)
#define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30)
#define S_SCD_L2ECC_CORR_D 0
#define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_D)
#define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_D)
#define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_D,M_SCD_L2ECC_CORR_D)
#define S_SCD_L2ECC_CORR_D 0
#define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_D)
#define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_D)
#define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_D,M_SCD_L2ECC_CORR_D)
#define S_SCD_L2ECC_BAD_D 8
#define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_D)
#define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_D)
#define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_D,M_SCD_L2ECC_BAD_D)
#define S_SCD_L2ECC_BAD_D 8
#define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_D)
#define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_D)
#define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_D,M_SCD_L2ECC_BAD_D)
#define S_SCD_L2ECC_CORR_T 16
#define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_T)
#define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_T)
#define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_T,M_SCD_L2ECC_CORR_T)
#define S_SCD_L2ECC_CORR_T 16
#define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_T)
#define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_T)
#define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_T,M_SCD_L2ECC_CORR_T)
#define S_SCD_L2ECC_BAD_T 24
#define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_T)
#define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_T)
#define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_T,M_SCD_L2ECC_BAD_T)
#define S_SCD_L2ECC_BAD_T 24
#define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_T)
#define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_T)
#define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_T,M_SCD_L2ECC_BAD_T)
#define S_SCD_MEM_ECC_CORR 0
#define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8,S_SCD_MEM_ECC_CORR)
#define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_CORR)
#define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_CORR,M_SCD_MEM_ECC_CORR)
#define S_SCD_MEM_ECC_CORR 0
#define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8,S_SCD_MEM_ECC_CORR)
#define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_CORR)
#define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_CORR,M_SCD_MEM_ECC_CORR)
#define S_SCD_MEM_ECC_BAD 16
#define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8,S_SCD_MEM_ECC_BAD)
#define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_BAD)
#define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_BAD,M_SCD_MEM_ECC_BAD)
#define S_SCD_MEM_ECC_BAD 8
#define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8,S_SCD_MEM_ECC_BAD)
#define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_BAD)
#define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_BAD,M_SCD_MEM_ECC_BAD)
#define S_SCD_MEM_BUSERR 24
#define M_SCD_MEM_BUSERR _SB_MAKEMASK(8,S_SCD_MEM_BUSERR)
#define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x,S_SCD_MEM_BUSERR)
#define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x,S_SCD_MEM_BUSERR,M_SCD_MEM_BUSERR)
#define S_SCD_MEM_BUSERR 16
#define M_SCD_MEM_BUSERR _SB_MAKEMASK(8,S_SCD_MEM_BUSERR)
#define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x,S_SCD_MEM_BUSERR)
#define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x,S_SCD_MEM_BUSERR,M_SCD_MEM_BUSERR)
/*
@ -367,7 +423,9 @@
#define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5)
#define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6)
#define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7)
#define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8) /* PASS2 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8)
#endif /* 1250 PASS2 || 112x PASS1 */
#define S_SCD_TRACE_CFG_CUR_ADDR 10
#define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR)

8
sys/arch/mips/sibyte/include/sb1250_smbus.h
View File

@ -149,11 +149,7 @@
#define V_SPEC_MB(x) _SB_MAKEVALUE(x,S_SPEC_PEC)
/* *********************************************************************
* PASS2 Extensions to SMBus
********************************************************************* */
/* BEGIN PASS2 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define S_SMB_CMDH 8
#define M_SMB_CMDH _SB_MAKEMASK(8,S_SMBH_CMD)
@ -186,6 +182,6 @@
#define V_SMB_DFMT_CMD5BYTE V_SMB_DFMT(K_SMB_DFMT_CMD5BYTE)
#define V_SMB_DFMT_RESERVED V_SMB_DFMT(K_SMB_DFMT_RESERVED)
/* END PASS2 */
#endif /* 1250 PASS2 || 112x PASS1 */
#endif

4
sys/arch/mips/sibyte/include/sb1250_uart.h
View File

@ -348,8 +348,9 @@
#define M_DUART_OUT_PIN_CLR(chan) \
(chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
/*
* Full Interrupt Control Register (PASS2)
* Full Interrupt Control Register
*/
#define S_DUART_SIG_FULL _SB_MAKE64(0)
@ -361,6 +362,7 @@
#define M_DUART_INT_TIME _SB_MAKEMASK(4,S_DUART_INT_TIME)
#define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x,S_DUART_INT_TIME)
#define G_DUART_INT_TIME(x) _SB_GETVALUE(x,S_DUART_INT_TIME,M_DUART_INT_TIME)
#endif /* 1250 PASS2 || 112x PASS1 */
/* ********************************************************************** */