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106 Commits

Author SHA1 Message Date
joerg
3fa00e0306 Avoid warnings for tautological shifts as sole conditional. 2019-10-28 18:11:15 +00:00
mlelstv
f0d950ca00 Skip setting power when the voltage doesn't change. 
Also increase some timeouts.
 2019-10-28 06:00:14 +00:00
hkenken
af57fdaa25 Add SDHC flags. 
+ SDHC_FLAG_BROKEN_ADMA2_ZEROLEN
  Broken ADMA2 Zero length descriptor.
  Can't 64K Byte data transfer.
+ SDHC_FLAG_NO_1_8_V
  Support no 1.8V Supply.
  Disable UHS-I bus speed mode (SDR50, DDR50, SDR104).
 2019-10-23 05:20:52 +00:00
jmcneill
1caa0d51d2 If switching to fixed sampling clock, do not return an error to the sdmmc layer. 2019-07-03 23:10:08 +00:00
jmcneill
16219c4edc Add vendor callback for post-bus clock ops and add SDHC_FLAG_STOP_WITH_TC flag 2019-03-13 12:16:49 +00:00
ryo
1f8d76d027 fix problem for ESDHC/USDHC due to change of r1.96 
on ESDHC/USDHC, even if the iosize is less than SDHC_HOST_CTL_VERSION,
specver must be an appropriate value.
 2017-06-23 08:43:59 +00:00
jmcneill
872a36d5d4 Add a vendor callback for setting signal voltage. 2017-04-22 21:49:41 +00:00
nonaka
7003a76595 sdhc(4): hardware reset support for Intel eMMC controller 2017-02-17 10:51:48 +00:00
nonaka
e7641d9af9 sdhc(4), sdmmc(4): Added MMC HS DDR52 support. 2017-02-17 10:50:43 +00:00
kiyohara
e741f78902 Add flags SDHC_FLAG_NO_AUTO_STOP and SDHC_FLAG_NO_BUSY_INTR. 2017-01-07 15:05:08 +00:00
kiyohara
322a2dc1e7 Don't access SDHC_HOST_CTL_VERSION, if iosize less than this. 2017-01-07 15:00:38 +00:00
nonaka
29e60e139c Use 1.65-1.95 voltage window for 1.8V support. 2016-08-10 04:24:17 +00:00
kiyohara
5c0f9a0541 Please more delay, if timeout in sdhc_wait_intr(). 2016-07-03 11:55:27 +00:00
ryo
1fc390a6bc add support iMX6 uSDHC 
- some UHS-I/SDR104 card are not stable
- eMMC doesn't work yet
 2015-12-31 11:53:18 +00:00
ryo
e92ba46909 fix typo. use pmask for SDHC_PRESENT_STATE. 2015-12-28 16:47:11 +00:00
mlelstv
066871a1c6 Also wait for DAT when sending RSP_BSY commands. Fixes PR 50388. 2015-11-03 07:59:29 +00:00
mlelstv
51893517ae fix timeout path in soft reset when building with SDHC_DEBUG 2015-11-03 06:49:39 +00:00
jmcneill
78131770be allow vendor specific code to hook into bus width changes 2015-11-02 22:18:45 +00:00
mlelstv
f30ec675b0 support hiding command timeout messages with a new command flag and use this 
when probing for cards. Should fix PR 50302.
 2015-10-06 14:32:51 +00:00
mlelstv
bf5ddae367 The iMX uSDHC controller doesn't have an interrupt error status flag, 
the bit position is reserved and reads as value 0.
- Fake the flag if any of the error bits is set.
- uSDHC supports the 32bit access, the 16bit path doesn't need that quirk.
 2015-09-09 08:09:28 +00:00
mlelstv
67a699c695 Don't test flags from error value in status value. Instead test the 
error interrupt status.
 2015-09-09 08:06:47 +00:00
mlelstv
e1ce7188c3 fix DPRINTF parameters 2015-09-09 08:04:33 +00:00
mlelstv
814eb59767 Ignore data inhibit for commands that do not use the DAT line. 
Do a soft reset when the inhibit condition persists for better
error recovery.

Simplify interrupt handling and print errors reported by the controller.

Add more specific debug messages for timeout errors.
 2015-08-09 13:46:50 +00:00
mlelstv
0684edc847 Protect the whole tuning operation including the register setup. 2015-08-09 13:39:18 +00:00
mlelstv
b33e86824b Add a quirk for Ricoh 5U823 controller. Operation with a 100MHz 
bus clock for SDR50 seems to be unstable, reduce frequency one notch
(effectively down to 66MHz with divisor = 3).
 2015-08-09 13:24:39 +00:00
jmcneill
cb3aabba92 don't hold intr_lock while calling sdhc_execute_tuning 2015-08-06 09:30:55 +00:00
jmcneill
03f2930ea5 support re-tuning modes 1 and 2 2015-08-05 12:28:47 +00:00
jmcneill
e5ced7d3cc Implement SDHC sampling clock tuning procedure. 2015-08-05 10:30:25 +00:00
mlelstv
b0f98a2aab lock more hardware accesses 2015-08-05 07:31:52 +00:00
jmcneill
7adf6ea00e Add SDHC_FLAG_POLL_CARD_DET flag which lets the bus glue request polling 
instead of standard SDHC card insert / detach events.
 2015-08-03 12:11:36 +00:00
jmcneill
9350eba507 Add support for DDR50 transfer modes. 2015-08-03 10:08:51 +00:00
mlelstv
fecfff5069 better error message 2015-08-03 05:24:37 +00:00
jmcneill
8fc8e58857 don't select SDR12 mode if we are <= 400 kHz 2015-08-03 00:44:52 +00:00
jmcneill
a9d443eb60 dont confuse signaling voltage and bus voltage 2015-08-03 00:19:27 +00:00
jmcneill
8055da5b7d let SDHC_FLAG_HOSTCAPS override SDHC_CAPABILITIES2 as well 2015-08-02 22:01:28 +00:00
jmcneill
30f521ffbf add support for UHS-I modes on capable 3.0+ controllers 2015-08-02 21:45:12 +00:00
jmcneill
bf94bade59 bus_dma_segment_t ds_addr is bus_addr_t not paddr_t (another case of it) 2015-08-02 11:28:01 +00:00
jmcneill
c753669c8d bus_dma_segment_t ds_addr is bus_addr_t not paddr_t 2015-08-02 11:26:21 +00:00
mlelstv
b296682ed1 Be more verbose about error conditions. 2015-08-02 07:14:10 +00:00
mlelstv
f89cb33206 correct (the commented out) calculation of bus frequency. 2015-08-02 07:07:02 +00:00
jmcneill
4c59c4959f return MMC_OCR_HCS bit from host_ocr if the controller supports high-speed mode 2015-08-02 00:24:24 +00:00
jmcneill
cd42d5bc1f Simplify sdhc(4) locking 2015-07-31 15:00:07 +00:00
jmcneill
9f711c8f1a print "platform DMA" instead of "SDMA" when using external DMA engine 2015-07-30 15:03:14 +00:00
jmcneill
e9e1d300f5 Add ADMA2 support, which enables scatter gather DMA for data transfers on 
controllers that support it.
 2015-07-29 12:11:13 +00:00
skrll
a356d4b44c Remove unnecessary #include 2015-07-28 07:14:48 +00:00
jmcneill
3cc75aa740 Add a SDHC_FLAG_NO_TIMEOUT quirk to handle spurious timeouts on Tegra K1 
during data transfers. While here, increase the soft timeout for DMA
transfers from 1s to 3s.
 2015-07-23 23:52:54 +00:00
skrll
ffeb9ab4ea Use C99 designated initializers. 
No functional change.
 2015-07-22 09:54:42 +00:00
jmcneill
53635e2272 support 8-bit mode for SDHC 3.0+ controllers 2015-05-30 17:52:07 +00:00
jmcneill
c82d0cfd23 print some useful information at attach time 2015-05-03 22:37:27 +00:00
jmcneill
e974ccfaa2 Add SDHC_FLAG_SINGLE_POWER_WRITE flag, that tells the driver to update 
the SDHC_POWER_CTL register with a single write rather than in multiple
steps. Required for Tegra K1 SDHC.
 2015-05-03 11:46:25 +00:00