Add a SDHC_FLAG_NO_TIMEOUT quirk to handle spurious timeouts on Tegra K1
during data transfers. While here, increase the soft timeout for DMA transfers from 1s to 3s.
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@ -1,4 +1,4 @@
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/* $NetBSD: sdhc.c,v 1.60 2015/07/22 09:54:42 skrll Exp $ */
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/* $NetBSD: sdhc.c,v 1.61 2015/07/23 23:52:54 jmcneill Exp $ */
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/* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */
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/*
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@ -23,7 +23,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.60 2015/07/22 09:54:42 skrll Exp $");
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__KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.61 2015/07/23 23:52:54 jmcneill Exp $");
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#ifdef _KERNEL_OPT
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#include "opt_sdmmc.h"
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@ -55,7 +55,7 @@ void sdhc_dump_regs(struct sdhc_host *);
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#define SDHC_COMMAND_TIMEOUT hz
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#define SDHC_BUFFER_TIMEOUT hz
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#define SDHC_TRANSFER_TIMEOUT hz
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#define SDHC_DMA_TIMEOUT hz
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#define SDHC_DMA_TIMEOUT (hz*3)
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struct sdhc_host {
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struct sdhc_softc *sc; /* host controller device */
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@ -1119,6 +1119,17 @@ sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd)
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mutex_exit(&hp->intr_mtx);
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}
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if (ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_TIMEOUT)) {
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const uint16_t eintr = SDHC_CMD_TIMEOUT_ERROR;
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if (cmd->c_data != NULL) {
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HCLR2(hp, SDHC_EINTR_SIGNAL_EN, eintr);
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HCLR2(hp, SDHC_EINTR_STATUS_EN, eintr);
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} else {
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HSET2(hp, SDHC_EINTR_SIGNAL_EN, eintr);
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HSET2(hp, SDHC_EINTR_STATUS_EN, eintr);
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}
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}
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/*
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* Start the MMC command, or mark `cmd' as failed and return.
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*/
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@ -1332,7 +1343,7 @@ sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd)
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if (hp->sc->sc_vendor_transfer_data_dma != NULL) {
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error = hp->sc->sc_vendor_transfer_data_dma(sc, cmd);
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if (error == 0 && !sdhc_wait_intr(hp,
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SDHC_TRANSFER_COMPLETE, SDHC_TRANSFER_TIMEOUT)) {
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SDHC_TRANSFER_COMPLETE, SDHC_DMA_TIMEOUT)) {
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error = ETIMEDOUT;
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}
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} else {
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@ -1,4 +1,4 @@
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/* $NetBSD: sdhcvar.h,v 1.18 2015/05/03 11:46:25 jmcneill Exp $ */
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/* $NetBSD: sdhcvar.h,v 1.19 2015/07/23 23:52:54 jmcneill Exp $ */
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/* $OpenBSD: sdhcvar.h,v 1.3 2007/09/06 08:01:01 jsg Exp $ */
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/*
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@ -54,6 +54,7 @@ struct sdhc_softc {
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#define SDHC_FLAG_EXTDMA_DMAEN 0x00008000 /* ext. dma need SDHC_DMA_ENABLE */
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#define SDHC_FLAG_NO_CLKBASE 0x00020000 /* ignore clkbase register */
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#define SDHC_FLAG_SINGLE_POWER_WRITE 0x00040000
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#define SDHC_FLAG_NO_TIMEOUT 0x00080000 /* ignore timeout interrupts */
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uint32_t sc_clkbase;
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int sc_clkmsk; /* Mask for SDCLK */
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