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Add a quirk for Ricoh 5U823 controller. Operation with a 100MHz 

bus clock for SDR50 seems to be unstable, reduce frequency one notch
(effectively down to 66MHz with divisor = 3).
This commit is contained in:
mlelstv 2015-08-09 13:24:39 +00:00
parent 0051183d01
commit b33e86824b
2 changed files with 13 additions and 3 deletions
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13
sys/dev/sdmmc/sdhc.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: sdhc.c,v 1.81 2015/08/06 09:30:55 jmcneill Exp $ */
/* $NetBSD: sdhc.c,v 1.82 2015/08/09 13:24:39 mlelstv Exp $ */
/* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */
/*
@ -23,7 +23,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.81 2015/08/06 09:30:55 jmcneill Exp $");
__KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.82 2015/08/09 13:24:39 mlelstv Exp $");
#ifdef _KERNEL_OPT
#include "opt_sdmmc.h"
@ -1071,6 +1071,15 @@ sdhc_bus_clock_ddr(sdmmc_chipset_handle_t sch, int freq, bool ddr)
}
}
/*
* Slow down Ricoh 5U823 controller that isn't reliable
* at 100MHz bus clock.
*/
if (ISSET(hp->sc->sc_flags, SDHC_FLAG_SLOW_SDR50)) {
if (freq == 100000)
--freq;
}
/*
* Set the minimum base clock frequency divisor.
*/

3
sys/dev/sdmmc/sdhcvar.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: sdhcvar.h,v 1.23 2015/08/03 12:11:36 jmcneill Exp $ */
/* $NetBSD: sdhcvar.h,v 1.24 2015/08/09 13:24:39 mlelstv Exp $ */
/* $OpenBSD: sdhcvar.h,v 1.3 2007/09/06 08:01:01 jsg Exp $ */
/*
@ -57,6 +57,7 @@ struct sdhc_softc {
#define SDHC_FLAG_NO_TIMEOUT 0x00080000 /* ignore timeout interrupts */
#define SDHC_FLAG_USE_ADMA2 0x00100000
#define SDHC_FLAG_POLL_CARD_DET 0x00200000 /* polling card detect */
#define SDHC_FLAG_SLOW_SDR50 0x00400000 /* reduce SDR50 speed */
uint32_t sc_clkbase;
int sc_clkmsk; /* Mask for SDCLK */