support re-tuning modes 1 and 2
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jmcneill
parent
e5ced7d3cc
commit
03f2930ea5
@ -1,4 +1,4 @@
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/* $NetBSD: sdhc.c,v 1.79 2015/08/05 10:30:25 jmcneill Exp $ */
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/* $NetBSD: sdhc.c,v 1.80 2015/08/05 12:28:47 jmcneill Exp $ */
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/* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */
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/*
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@ -23,7 +23,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.79 2015/08/05 10:30:25 jmcneill Exp $");
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__KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.80 2015/08/05 12:28:47 jmcneill Exp $");
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#ifdef _KERNEL_OPT
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#include "opt_sdmmc.h"
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@ -36,6 +36,7 @@ __KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.79 2015/08/05 10:30:25 jmcneill Exp $");
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#include <sys/systm.h>
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#include <sys/mutex.h>
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#include <sys/condvar.h>
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#include <sys/atomic.h>
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#include <dev/sdmmc/sdhcreg.h>
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#include <dev/sdmmc/sdhcvar.h>
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@ -78,6 +79,11 @@ struct sdhc_host {
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kmutex_t intr_lock;
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kcondvar_t intr_cv;
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callout_t tuning_timer;
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int tuning_timing;
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u_int tuning_timer_count;
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u_int tuning_timer_pending;
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int specver; /* spec. version */
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uint32_t flags; /* flags for this host */
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@ -184,6 +190,7 @@ static void sdhc_exec_command(sdmmc_chipset_handle_t,
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struct sdmmc_command *);
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static int sdhc_signal_voltage(sdmmc_chipset_handle_t, int);
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static int sdhc_execute_tuning(sdmmc_chipset_handle_t, int);
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static void sdhc_tuning_timer(void *);
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static int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *);
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static int sdhc_wait_state(struct sdhc_host *, uint32_t, uint32_t);
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static int sdhc_soft_reset(struct sdhc_host *, int);
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@ -279,6 +286,8 @@ sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot,
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mutex_init(&hp->intr_lock, MUTEX_DEFAULT, IPL_SDMMC);
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cv_init(&hp->intr_cv, "sdhcintr");
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callout_init(&hp->tuning_timer, CALLOUT_MPSAFE);
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callout_setfunc(&hp->tuning_timer, sdhc_tuning_timer, hp);
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if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
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sdhcver = HREAD4(hp, SDHC_ESDHC_HOST_CTL_VERSION);
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@ -329,6 +338,18 @@ sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot,
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}
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}
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const u_int retuning_mode = (caps2 >> SDHC_RETUNING_MODES_SHIFT) &
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SDHC_RETUNING_MODES_MASK;
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if (retuning_mode == SDHC_RETUNING_MODE_1) {
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hp->tuning_timer_count = (caps2 >> SDHC_TIMER_COUNT_SHIFT) &
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SDHC_TIMER_COUNT_MASK;
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if (hp->tuning_timer_count == 0xf)
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hp->tuning_timer_count = 0;
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if (hp->tuning_timer_count)
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hp->tuning_timer_count =
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1 << (hp->tuning_timer_count - 1);
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}
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/*
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* Use DMA if the host system and the controller support it.
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* Suports integrated or external DMA egine, with or without
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@ -442,6 +463,11 @@ sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot,
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SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V);
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aprint_normal(" 3.3V");
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}
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if (hp->specver >= SDHC_SPEC_VERS_300) {
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aprint_normal(", re-tuning mode %d", retuning_mode + 1);
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if (hp->tuning_timer_count)
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aprint_normal(" (%us timer)", hp->tuning_timer_count);
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}
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/*
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* Determine the maximum block length supported by the host
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@ -560,6 +586,7 @@ adma_done:
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return 0;
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err:
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callout_destroy(&hp->tuning_timer);
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cv_destroy(&hp->intr_cv);
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mutex_destroy(&hp->intr_lock);
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free(hp, M_DEVBUF);
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@ -595,6 +622,8 @@ sdhc_detach(struct sdhc_softc *sc, int flags)
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sdhc_soft_reset(hp, SDHC_RESET_ALL);
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mutex_exit(&hp->intr_lock);
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}
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callout_halt(&hp->tuning_timer, NULL);
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callout_destroy(&hp->tuning_timer);
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cv_destroy(&hp->intr_cv);
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mutex_destroy(&hp->intr_lock);
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if (hp->ios > 0) {
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@ -841,6 +870,7 @@ sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr)
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/* If power is disabled, reset the host and return now. */
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if (ocr == 0) {
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(void)sdhc_host_reset1(hp);
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callout_halt(&hp->tuning_timer, &hp->intr_lock);
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goto out;
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}
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@ -1241,6 +1271,8 @@ sdhc_execute_tuning(sdmmc_chipset_handle_t sch, int timing)
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uint8_t hostctl;
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int opcode, error, retry = 40;
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hp->tuning_timing = timing;
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switch (timing) {
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case SDMMC_TIMING_MMC_HS200:
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opcode = MMC_SEND_TUNING_BLOCK_HS200;
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@ -1318,9 +1350,22 @@ sdhc_execute_tuning(sdmmc_chipset_handle_t sch, int timing)
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return EIO; /* tuning failed */
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}
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if (hp->tuning_timer_count) {
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callout_schedule(&hp->tuning_timer,
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hz * hp->tuning_timer_count);
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}
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return 0; /* tuning completed */
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}
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static void
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sdhc_tuning_timer(void *arg)
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{
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struct sdhc_host *hp = arg;
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atomic_swap_uint(&hp->tuning_timer_pending, 1);
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}
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static int
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sdhc_wait_state(struct sdhc_host *hp, uint32_t mask, uint32_t value)
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{
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@ -1345,6 +1390,10 @@ sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd)
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mutex_enter(&hp->intr_lock);
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if (atomic_cas_uint(&hp->tuning_timer_pending, 1, 0) == 1) {
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(void)sdhc_execute_tuning(hp, hp->tuning_timing);
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}
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if (cmd->c_data && ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
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const uint16_t ready = SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY;
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if (ISSET(hp->flags, SHF_USE_DMA)) {
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@ -2096,6 +2145,13 @@ sdhc_intr(void *arg)
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}
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}
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/*
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* Schedule re-tuning process (UHS).
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*/
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if (ISSET(status, SDHC_RETUNING_EVENT)) {
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atomic_swap_uint(&hp->tuning_timer_pending, 1);
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}
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/*
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* Wake up the blocking process to service command
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* related interrupt(s).
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@ -1,4 +1,4 @@
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/* $NetBSD: sdhcreg.h,v 1.16 2015/08/05 10:30:25 jmcneill Exp $ */
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/* $NetBSD: sdhcreg.h,v 1.17 2015/08/05 12:28:47 jmcneill Exp $ */
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/* $OpenBSD: sdhcreg.h,v 1.4 2006/07/30 17:20:40 fgsch Exp $ */
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/*
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@ -112,6 +112,7 @@
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#define SDHC_RESET_ALL (1<<0)
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#define SDHC_NINTR_STATUS 0x30
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#define SDHC_ERROR_INTERRUPT (1<<15)
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#define SDHC_RETUNING_EVENT (1<<12)
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#define SDHC_CARD_INTERRUPT (1<<8)
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#define SDHC_CARD_REMOVAL (1<<7)
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#define SDHC_CARD_INSERTION (1<<6)
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@ -121,7 +122,7 @@
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#define SDHC_BLOCK_GAP_EVENT (1<<2)
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#define SDHC_TRANSFER_COMPLETE (1<<1)
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#define SDHC_COMMAND_COMPLETE (1<<0)
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#define SDHC_NINTR_STATUS_MASK 0x81ff
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#define SDHC_NINTR_STATUS_MASK 0x91ff
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#define SDHC_EINTR_STATUS 0x32
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#define SDHC_DMA_ERROR (1<<12)
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#define SDHC_ADMA_ERROR (1<<9)
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@ -190,6 +191,9 @@
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#define SDHC_TUNING_SDR50 (1<<13)
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#define SDHC_RETUNING_MODES_SHIFT 14
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#define SDHC_RETUNING_MODES_MASK 0x3
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#define SDHC_RETUNING_MODE_1 (0 << SDHC_RETUNING_MODES_SHIFT)
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#define SDHC_RETUNING_MODE_2 (1 << SDHC_RETUNING_MODES_SHIFT)
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#define SDHC_RETUNING_MODE_3 (2 << SDHC_RETUNING_MODES_SHIFT)
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#define SDHC_CLOCK_MULTIPLIER_SHIFT 16
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#define SDHC_CLOCK_MULTIPLIER_MASK 0xff
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#define SDHC_ADMA_ERROR_STATUS 0x54
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