* Use a common set of exception handlers for all arm32 platforms.
* New FIQ framework based on discussions with Ben Harris, shared
between arm26 and arm32.
<arm/arm32/vmparam.h> (mostly the stuff that's tied to the pmap
implementation).
- Since the MMU definitions in pte.h are specific to ARM processors
that support 32-bit mode, move pte.h to <arm/arm32/pte.h>.
- Make the Netwinder startup file build again (use PT_B|PT_C, rather
than PT_CACHEABLE, since the latter expands to a variable these days).
model in use for a given platform (__PROG26 vs __PROG32), then pulls
in <arm/types.h>. Change each ARM port to pull in <arm/arm26/types.h>
or <arm/arm32/types.h> as appropriate. Change all references to PROG26
and PROG32 to __PROG26 and __PROG32. Eliminate the opt_progmode.h
header file.
this insn is available only on ARM arch v3 and later (and 2a). We
don't expect to be using these ops in the kernel on processors too
old to have SWP, and for userland uses (in e.g. a pthread library),
the kernel will simply have to trap and emulate the insn (it needs
to be "atomic", so a kernel trap of some sort will be necessary on
such platforms anyway).
the Branch Target Buffer of the BPRD bit changes.
* Enable Branch Prediction on the XScale by default.
* Don't invalidate the Branch Target Buffer explicitly. the i80200
manual (section 5.1, Branch Target Buffer Operation) notes that
manual software management of the BTB is unnecessary; it is flushed
implicitly when:
* processor resets
* FCSE process ID is written
* I-cache is invalidated
pages, we use the standard (4K) page size as PAGE_SIZE. Make the
PAGE_SIZE related variables compile-time constants that reflect this.
Results in a bit over 2K worth of .text savings, and visibly better
code in the places that use PAGE_SIZE, etc.
support it in the kernel yet. If we don't do this, GDB arbitrarily
assumes we wanted it to be 9, which is silly.
In the kernel, leave it undefined so that sys_process.c doesn't
generate code for it.
the instruction we used with GDB 4.x. The new instruction has the advantage
of fitting the pattern that ARM recommend using for instructions that need to
stay undefined.
This will allow improvements to the pmaps so that they can more easily defer expensive operations, eg tlb/cache flush, til the last possible moment.
Currently this is a no-op on most platforms, so they should see no difference.
Reviewed by Jason.
Thorpe as an extension to the bus_space(9) API.
Only the mainbus has a working mmap... iomd, podulebus and isa dont have
one yet. Its trivial to add the iomd and isa's memory part but am a bit
hessistant to add it without knowing its implications by heart.
Podulebus might be implemented in 32 bits EASI but otherwise its not really
transparent since there is AFAIK no function to explicitly read one byte or
so .. or is this implemented in a higher level ?
ARM26 and arch/arm32/dnard (Shark) kernels compile and RiscPC and Shark
kernels are tested and function OK.
Implications of other ARM systems like hpcarm and ebarm are propably
minimal or solved trivially.
Improved locking (not that we actually use it on a uniprocessor, but one day :)
Removed unneeded splvm's
tweaked pmap_clean_page code to only flush the cache if the page is mapped in the current pmap (based on diff from richard E)
Adopted pv entry allocation mechanism from i386.
Laid framework for returning ptp's when we've finished with them rather than holding onto them till the process exits.
ptp's are now allocated with a uvm object for the pmap, means that we can walk a list to free them off in pmap_release, until they get freed off by pmap_remove.
Also implemented a page zeroing function when the processor is idling. Note that hpcarm may wish to disable this.
I believe this code to be stable, if anyone has any problems please shout up.
thorpej