They do not seem well-justified according to anyone's understanding
of what they really do, and it seems especially inappropriate to
call them at attach- and resume-time.
get rid of SIP_DECL() and reduce #ifdef DP83820 code. Next step
is to move a bunch of shared code to a new file (if_sipcom.c, say)
and compile it *once*.
While I am here, add suspend/resume handling to sip(4) and to
gsip(4).
Tested with the NatSemi sip(4) on the Soekris net4521. I don't
have any gsip(4) to test with, and it seems that the few holders
of gsip(4) in the world keep them in their attic, anyway.
I don't know why we gpio(4) didn't do that before, but it seems
harmless.
Add naive power handling: when a gpio(4) instance is resumed, write
each pin's configuration flags and output state from the softc to
the hardware using gpiobus_pin_ctl() and gpiobus_pin_write().
While suspended, fail every ioctl() except for GPIOINFO with EBUSY.
separate powering up devices from restoring their state. This is required
on some machines where AcpiLeaveSleepState can fail due to an attempt to
access a powered off device.
82571 manual and Intel Application Note 450. Previously, we were setting
RADV and TIDV/TADV values that didn't make any sense given the enormous
ITR value we were setting (well outside the range recommended by Intel
and quite possibly rejected silently by the chip as junk) and setting
RADV without setting RDTR, which is explicitly documented as having no
effect.
A considerable performance improvement is achieved for TCP and UDP at
gigabit speed. I need to revisit this to deal with the timer ticks
being 4X as long when the chip's in 100mbit mode, and to set values
for the older chips' interrupt timers that are more like what the
appnote recommends. This should help for 82543 and newer, though.
system was before on resume. This is the second attempt and got more
complicated due to the async nature of VT_ACTIVE. After the initial
switch, check that we ended up on the first screen and if not, wait for
the switch to happen.
Rev 1.41:
> use a nop with I bit set at the end of the tx chain. This avoids a race
> between status update and clearing the suspend bit on machines which can't
> write data smaller than 32bits at a time.
This should fix PR port-alpha/30560.
Rev 1.50:
> Fix nasty bug where driver would not correctly catch and handle an rnr
> condition when it was due to the the recieve buffers being exhausted with
> no packet transmits during that time. Symptom was that the fxp would
> simply stop interrupting for the next 15 seconds until the watchdog kicked
> in and reset the chip due to 15 seconds of inactivity, making the fxp very
> poorly behaved when hammered on hard.
Rev 1.61:
> Defer reinitialisation of the RU until after the interrupt handler has had
> a chance to process all pending packets, otherwise the chip may overwrite
> their mbuf clusters after we have freed them.
>
> Eliminates a race that can cause random pool corruption when reconfiguring
> an interface under heavy network load.
And one more change for RX sanity:
- put RU into suspend when the last RFA is processed.
These RNR/RU changes may fix pool corruption problems on fxp.
Tested on AlphaPC164 and i386 with i82559 and i82550.
volumes that are migrating such as when you change the stripe size.
While I'm here use the same string than we had in the old framework to
report status "online" vs "drive is online", because the sensor might be
a RAID volume and not just a drive.
- malloc(9) -> kmem(9) now that most of the bio code doesn't need to run
on interrupt context.
- Reduce code that runs in interrupt context to a small part in
arc_msgbuf() and is protected by arc_lock()/arc_unlock().
Reviewed and help by ad@.
break functionality. I've tested this on a PCIE R423 (X800).
- In drm_drv.c, check that the requested context lock matches the holder
of the lock.
- Unify radeon offset checking. (r300_cmdbuf.c, radeon_drv.h, radeon_state.c)
[Replace r300_check_offset() with generic radeon_check_offset(), which doesn't
reject valid offsets when the framebuffer area is at the very end of the card's
32 bit address space. Make radeon_check_and_fixup_offset() use
radeon_check_offset() as well.
This fixes https://bugs.freedesktop.org/show_bug.cgi?id=7697]
NOTE: There is another AGP fix that I didn't have time to merge
that I thought might help with getting this to work on macppc.
Contact me if you're interested. Hi macallan@! ;)
radeon_cp.c, radeon_drv.h: (GIT id: bb5f2158dbd30dbbffa3881fac75b71d71ecaaf9)
- set the address to access the aperture on the CPU side correctly
[This code relied on the CPU and GPU address for the aperture being the same,
On some r5xx hardware I was playing with I noticed that this isn't always true.
I wonder if this will fix some of those r4xx DRI issues we've seen in the past.]
- Commit the ring after earch partial texture. (radeon_state.c)
(GIT ID: ac8406420ea80ffe5ccaadc1ff0124f95709a23d)
[Commit the ring after each partial texture upload blit.
This makes sure each blit starts as early as possible, which may improve
texture upload performance in some cases.]
If anyone's having any issues in particular--especially those which
can be _teased apart from AGP driver issues--please let me know
and I'll investigate. Thanks. There are also tons of fixes for the i915,
but I don't want to change too much at once.
this fixes a panic with debugging options.
- Do not use a callout to refresh sensor data, and make it available
every time someone requests it.
- Enable ENVSYS_FMONSTCHANGED for notifications in the volumes.
(nForce 2/3/4).
nfsmb(4) is now properly working on newer MCPs, tested by wiz@ on MCP55:
nfsmbc0 at pci0 dev 1 function 1: NVIDIA nForce MCP55 SMBus Controller (rev. 0xa2)
nfsmb0 at nfsmbc0 SMBus 1
iic0 at nfsmb0: I2C bus
spdmem0 at iic0 addr 0x51
spdmem0: DDR2 SDRAM memory, data ECC, 1024MB, 667MHz, PC2-5300
spdmem0: 14 rows, 10 cols, 2 ranks, 4 banks/chip, 3.00ns cycle time
spdmem0: voltage SSTL 1.8V, refresh time 7.8us (self-refreshing)
nfsmb1 at nfsmbc0 SMBus 2
iic1 at nfsmb1: I2C bus
Fix the bus_dma(9) use in drm_pci.c and chnage struct drm_dma_handle_t
to match it. Remove member dmaaddr from drm_dma_handle_t as well,
as I don't see it used anywhere. Compile-tested only for now; please
report any problems to me. Thanks.
- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.
Buffers run through copy-on-write are marked B_COWDONE. This condition
is valid until the buffer has run through bwrite() and gets cleared from
biodone().
Welcome to 4.99.39.
Reviewed by: YAMAMOTO Takashi <yamt@netbsd.org>
