Make all the kernels that currently include their corresponding GENERIC.local
file use the cinclude directive instead of include. This way config(1) will
not complain if the file cannot be found.
After doing this, remove the GENERIC.local files from the repository so that
the user will not see modified files during updates, and local changes to
them cannot end up in the repository by mistake.
Discussed in tech-kern@ earlier this month. No strong objections.
them in the mi "files" file, and remove include statements from md files.
These shouldn't pull in additional kernel code when not in use, so it
shouldn't do any harm except a risk of namespace collisions which
should be easy to fix.
possibility of running on an MPC601, are infected with all the extra code
and nops that it added.
Also, fix compilation that I broke with the pmap code, by adding
oeacpufeat to the locores of various ppc arches. Noted by mlelstv.
- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.
SEMMNI, SEMMNS, SEMUME and SHMMAXPGS.
They can be tweaked via sysctl now. Ports that were setting values on
them weren't touched, I only removed the ones that were commented out.
This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.
TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.
NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
based machine. When we do, we have to frob a few special bits on the
pcib to finish the setup that the prom didn't bother completing for us.
With this change, NetBSD finally runs on the MTX604 board.. Many thanks
to John Baker for providing remote access to the machine, and rebooting
it repeatedly for me.
on the pin, to get us the right pin on the underlying PReP bridge to wire
the interrupt to. Tested with a 4-port fxp card on a 7043-140. Thanks
to simon for helping me get the math right.
associated with this, 0, the nvram device, and now 1, the residual
device. The devices allow the user to directly read the contents of the
kernel copy of the nvram, and the residual data respectively. There is
no provision for write.
actually contains entries. It is apparently possible to get a non-null,
but empty dictionary back. This seems to happen if you inject a ppb-card
on pci0 when you also have a prep pci1 at a later device function. With
this, my fxp card works in any slot on my 7043-140.
locators for uhub because a hub can't have sub-devices.
This might be sanity-checked eventually.
Same for ubt now after the change to device attachment.
(/dev/nvram) and implement all the associated ioctls fully. Tested with
a hacked up copy of eeprom(8). Right now it can only be used to see the
nvram GEV contents, not actually edit them. Will do that later some day.
- finish implementing splraiseipl (and makeiplcookie).
http://mail-index.NetBSD.org/tech-kern/2006/07/01/0000.html
- complete workqueue(9) and fix its ipl problem, which is reported
to cause audio skipping.
- fix netbt (at least compilation problems) for some ports.
- fix PR/33218.
long standing issue with interrupts onthe PowerStack E1. Remove the
quirk entry for the PowerStack E1 and revert to using the IVR.
Also, add a \n to the attachment of the mk clock printf that was missing.
by the initial PCI_NETBSD_CONFIGURE, nor should it be manually wired by
the indirect stuff. This is all taken care of by the prep_init() function.
7025-F40 support supports the primary pci bus only. The second PCI bus
on the machine is still unsupported, but the machine runs and can access
everything except for the two slots the other bus covers.
The bug displayed itself by locking up console output on a 7043-140
following a powercycle. This may also have been the cause of bogus
interrupts on motorola class machines.
for quite some time. Add it to all systems that have pcmcia SCSI.
Pointed out by Björn Johannesson <rherdware@yahoo.com> in private mail,
OK'd by matt@
try to locate it using the residual data. On some machines this doesn't
work, so we fall back to hardcoding it. This should fix isa interrupts
on the 7025-F40, which has the IVR at a different location.
out how to properly reboot these machines, instead we make use of the
auto-poweron-alarm time, and power cycle the machine to simulate a
reboot. This is a hack, but until I get documentation on these machines,
at least you will be able to reboot them.
for a magical PCI device location (that is sometimes wrong), we scan the
residual data for an MPIC, and if we find one, wire it up from there.
This will hopefully allow interrupts to work on the MPC750 and the
7025-F40. I suspect however the interrupt vector address on the 7025 will
still need some work.
1) Fix support for the powerstack E1. This machine needs to use the 8259
directly, and cannot use the prep interrupt vector register. Place a
quirk entry in the table for the machine.
2) Add a new com0_vreset boot image. The vreset code only works on a few
machines, and breaks others like the 7025-F40. Its only limitedly useful
when used with the com0, so just make it an optional image the user can
install by hand if they want.
3) Bump the bootloader to 1.8 with the above change.
2) Modify pnpbus attachment code to record the chipid of the device if it
has one.
3) Change the clock probes to use the chipid, rather than relying on
potentially untrustworthy subtype and interface.
4) Add decoding of memory ranges to the RESIDUAL_DUMP code.
5) Add a we@pnpbus device to allow netbooting and root device detection
from an IBM we ethernet. (it will only work if your firmware detects it)
6) Because I moved the pnpbus probe to occur prior to pci and isa, it
screwed up the root device detection and firmware path building code.
Completely rewrite the fw-path detection code to deal with this.
and INSTALL_SMALL. Since floppy images have to fit on one floppy, we
have to really cut down on the drivers on that image, but people
netbooting don't have that problem, so they deserve a more featured
kernel to install with. (namely one with raid support and more ethernet
drivers)
ntp on my 7248, however, my 7043-140 is still a bit flaky. I suspect the
only way to fix the 7043 is going to be writing a timecounter driver for
the 8254 present on these machines. Either way, this makes some of the
machines better, and the other machines are still about the same as they
were before, so it's a net gain for the port.
residual with the pnpbus probes, than it is to do it with raw isa probes,
so I've replaced the isa mkclock and mcclock code with a pnpbus attachment.
While writing the mkclock code, I realized that on motorola prep machines
the mkclock uses the same port range as the nvram part. (it's actually
the same chip/part). This was causing the nvram not to work on those
machines. Now the nvram code will recognize this, and wire up the
mkclock as well. The mkclock probe is just a stub probe used to
pre-detect the fact that this is one of those machines.
1) Rather than build an array of the pci->intr mappings, build a proplib
tree.
2) add a SIMPLEQ of device properties to the pci_chipset_tag to hold the
proplib trees of each bus.
3) Move the interrupt routing code from pci_conf_interrupt to pci_map_intr()
4) Deal properly with non-native PCI bridge chips that are not recognized
by the prep firmware, and therefore are not noted in the residual data.
The major win of this restructure is #4. Hopefully I haven't broken
anything. Tested on a 7248-100, 7043-140 and 7024-E20.
proper pcipnp structure file to read them rather than magical array offsets.
Add more complete decoding of the VPD, including extendedvpd, and TLB. While
I was here, fix a bug where we never printed the L1 cache data properly.
models. This code was made possible by assistance from Cory Bajus.
Add code that asks the PCI bridge what it's config base address is, and
use that when wiring up an indirect bridge type.
Move prep's user segment register to 10, because the 7025's PCI config
address is at 11, where the user segment used to be.
Add a battable entry for 0xbf800000 for machines with RS6K bridges.
There is still probably work left to be done before a 7025-F40 is fully
supported.
1) The E1 seems to have the int. siop wired to irq 14-level and the internal
wdc wired to irq 14-edge. special case and fail the wdc probe on E1's.
2) If we fail to map the NVRAM registers, return, rather than trying to talk
to them and panic'ing the box.
3) revert my previous "fix" to pnpbus to make irq's default to level. It
was wrong, and didn't even fix the powerstack.
With this, we have limited PowerStack E1 support. The machine cannot
talk to it's IDE controller, and cannot detect it's boot device
automatically, but it does come up and run. Tested with NFS root.
cube