Switch prep over to evcnt(9). While I was here, I also switched it to
use struct cpu_info for the cpu stuff. Tested on 7248 and 7043.
This commit is contained in:
garbled
parent
3ce69693c2
commit
be39d7253e
@ -1,4 +1,4 @@
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/* $NetBSD: intr.h,v 1.24 2006/05/03 17:47:06 garbled Exp $ */
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/* $NetBSD: intr.h,v 1.25 2006/05/08 17:08:34 garbled Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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@ -62,6 +62,7 @@
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#ifndef _LOCORE
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#include <powerpc/softintr.h>
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#include <machine/cpu.h>
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/*
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* Interrupt handler chains. intr_establish() inserts a handler into
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@ -76,6 +77,21 @@ struct intrhand {
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int ih_irq;
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};
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#include <sys/device.h>
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struct intrsource {
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int is_type;
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int is_level;
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int is_hwirq;
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int is_mask;
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struct intrhand *is_hand;
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struct evcnt is_ev;
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char is_source[16];
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};
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int splraise(int);
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int spllower(int);
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void softintr(int);
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void do_pending_int(void);
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void init_intr(void);
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@ -95,61 +111,14 @@ void isa_intr_mask(int);
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void isa_intr_clr(int);
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void isa_setirqstat(int, int, int);
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static __inline int splraise(int);
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static __inline void spllower(int);
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static __inline void set_sint(int);
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extern volatile int cpl, ipending, astpending, tickspending;
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extern int imen;
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extern int imask[];
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extern long intrcnt[];
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extern unsigned intrcnt2[];
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extern struct intrhand *intrhand[];
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extern int intrtype[];
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extern vaddr_t prep_intr_reg;
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/*
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* Reorder protection in the following inline functions is
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* achieved with the "eieio" instruction which the assembler
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* seems to detect and then doesn't move instructions past....
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*/
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static __inline int
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splraise(int newcpl)
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{
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int oldcpl;
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__asm volatile("sync; eieio\n"); /* don't reorder.... */
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oldcpl = cpl;
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cpl = oldcpl | newcpl;
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__asm volatile("sync; eieio\n"); /* reorder protect */
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return(oldcpl);
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}
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static __inline void
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spllower(int newcpl)
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{
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__asm volatile("sync; eieio\n"); /* reorder protect */
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cpl = newcpl;
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if(ipending & ~newcpl)
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do_pending_int();
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__asm volatile("sync; eieio\n"); /* reorder protect */
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}
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/* Following code should be implemented with lwarx/stwcx to avoid
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* the disable/enable. i need to read the manual once more.... */
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static __inline void
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set_sint(int pending)
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{
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int msrsave;
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__asm ("mfmsr %0" : "=r"(msrsave));
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__asm volatile ("mtmsr %0" :: "r"(msrsave & ~PSL_EE));
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ipending |= pending;
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__asm volatile ("mtmsr %0" :: "r"(msrsave));
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}
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#define ICU_LEN 32
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extern struct intrsource intrsources[ICU_LEN];
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#define IRQ_SLAVE 2
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#define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != IRQ_SLAVE)
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#define I8259_INTR_NUM 16
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@ -185,9 +154,9 @@ set_sint(int pending)
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#define spllpt() spltty()
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#define setsoftclock() set_sint(SINT_CLOCK);
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#define setsoftnet() set_sint(SINT_NET);
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#define setsoftserial() set_sint(SINT_SERIAL);
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#define setsoftclock() softintr(SINT_CLOCK);
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#define setsoftnet() softintr(SINT_NET);
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#define setsoftserial() softintr(SINT_SERIAL);
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#define splhigh() splraise(imask[IPL_HIGH])
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#define splsched() splhigh()
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@ -1,4 +1,4 @@
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/* $NetBSD: isa_machdep.c,v 1.9 2005/12/11 12:18:47 christos Exp $ */
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/* $NetBSD: isa_machdep.c,v 1.10 2006/05/08 17:08:34 garbled Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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@ -71,7 +71,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: isa_machdep.c,v 1.9 2005/12/11 12:18:47 christos Exp $");
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__KERNEL_RCSID(0, "$NetBSD: isa_machdep.c,v 1.10 2006/05/08 17:08:34 garbled Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -177,17 +177,17 @@ void
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init_icu(int lvlmask)
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{
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int i;
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extern int intrtype[];
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struct intrsource *is;
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for (i= 0; i < ICU_LEN; i++) {
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for (i = 0, is = intrsources; i < ICU_LEN; i++, is++) {
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switch (i) {
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case 0:
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case 2:
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case 8:
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intrtype[i] = IST_EDGE;
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is->is_type = IST_EDGE;
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break;
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default:
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intrtype[i] = (1 << i) & lvlmask ? IST_LEVEL : IST_NONE;
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is->is_type = (1 << i) & lvlmask ? IST_LEVEL : IST_NONE;
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}
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}
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@ -239,18 +239,21 @@ isa_intr_alloc(isa_chipset_tag_t c, int mask, int type, int *irq_p)
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int irq;
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int maybe_irq = -1;
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int shared_depth = 0;
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struct intrsource *is;
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mask &= 0x8b28; /* choose from 3, 5, 8, 9, 11, 15 XXX */
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for (irq = 0; mask != 0; mask >>= 1, irq++) {
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for (irq = 0, is = intrsources; mask != 0; mask >>= 1, irq++, is++) {
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if ((mask & 1) == 0)
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continue;
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if (intrtype[irq] == IST_NONE) {
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if (is->is_type == IST_NONE) {
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*irq_p = irq;
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return 0;
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}
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/* Level interrupts can be shared */
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if (type == IST_LEVEL && intrtype[irq] == IST_LEVEL) {
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struct intrhand *ih = intrhand[irq];
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if (type == IST_LEVEL && is->is_type == IST_LEVEL) {
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struct intrhand *ih = is->is_hand;
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int depth;
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if (maybe_irq == -1) {
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maybe_irq = irq;
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continue;
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@ -1,4 +1,4 @@
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/* $NetBSD: clock.c,v 1.13 2005/12/24 22:45:36 perry Exp $ */
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/* $NetBSD: clock.c,v 1.14 2006/05/08 17:08:34 garbled Exp $ */
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/* $OpenBSD: clock.c,v 1.3 1997/10/13 13:42:53 pefo Exp $ */
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/*
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@ -33,7 +33,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.13 2005/12/24 22:45:36 perry Exp $");
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__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.14 2006/05/08 17:08:34 garbled Exp $");
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#include <sys/param.h>
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#include <sys/kernel.h>
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@ -53,7 +53,6 @@ void decr_intr __P((struct clockframe *));
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u_long ticks_per_sec;
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u_long ns_per_tick;
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static long ticks_per_intr;
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static volatile u_long lasttb;
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struct device *clockdev;
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const struct clockfns *clockfns;
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@ -78,13 +77,14 @@ todr_attach(handle)
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void
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cpu_initclocks()
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{
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struct cpu_info * const ci = curcpu();
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ticks_per_intr = ticks_per_sec / hz;
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cpu_timebase = ticks_per_sec;
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if ((mfpvr() >> 16) == MPC601)
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__asm volatile ("mfspr %0,%1" : "=r"(lasttb) : "n"(SPR_RTCL_R));
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__asm volatile ("mfspr %0,%1" : "=r"(ci->ci_lasttb) : "n"(SPR_RTCL_R));
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else
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__asm volatile ("mftb %0" : "=r"(lasttb));
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__asm volatile ("mftb %0" : "=r"(ci->ci_lasttb));
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__asm volatile ("mtdec %0" :: "r"(ticks_per_intr));
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}
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@ -170,12 +170,12 @@ void
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decr_intr(frame)
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struct clockframe *frame;
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{
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struct cpu_info * const ci = curcpu();
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int msr;
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int pri;
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u_long tb;
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long ticks;
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int nticks;
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extern long intrcnt[];
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/*
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* Check whether we are initialized.
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@ -193,14 +193,14 @@ decr_intr(frame)
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__asm volatile ("mtdec %0" :: "r"(ticks));
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uvmexp.intrs++;
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intrcnt[CNT_CLOCK]++;
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ci->ci_ev_clock.ev_count++;
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pri = splclock();
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if (pri & SPL_CLOCK) {
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tickspending += nticks;
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ci->ci_tickspending += nticks;
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} else {
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nticks += tickspending;
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tickspending = 0;
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nticks += ci->ci_tickspending;
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ci->ci_tickspending = 0;
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/*
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* lasttb is used during microtime. Set it to the virtual
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@ -211,7 +211,7 @@ decr_intr(frame)
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} else {
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__asm volatile ("mftb %0" : "=r"(tb));
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}
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lasttb = tb + ticks - ticks_per_intr;
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ci->ci_lasttb = tb + ticks - ticks_per_intr;
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/*
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* Reenable interrupts
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@ -249,7 +249,7 @@ microtime(tvp)
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__asm volatile ("mfspr %0,%1" : "=r"(tb) : "n"(SPR_RTCL_R));
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else
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__asm volatile ("mftb %0" : "=r"(tb));
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ticks = (tb - lasttb) * ns_per_tick;
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ticks = (tb - curcpu()->ci_lasttb) * ns_per_tick;
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*tvp = time;
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__asm volatile ("mtmsr %0" :: "r"(msr));
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ticks /= 1000;
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu.c,v 1.12 2006/03/09 20:17:28 garbled Exp $ */
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/* $NetBSD: cpu.c,v 1.13 2006/05/08 17:08:34 garbled Exp $ */
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/*-
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* Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
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@ -37,7 +37,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.12 2006/03/09 20:17:28 garbled Exp $");
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__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.13 2006/05/08 17:08:34 garbled Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -71,7 +71,11 @@ cpumatch(struct device *parent, struct cfdata *cfdata, void *aux)
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void
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cpuattach(struct device *parent, struct device *self, void *aux)
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{
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cpu_attach_common(self, 0);
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struct cpu_info *ci;
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ci = cpu_attach_common(self, 0);
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if (ci == NULL)
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return;
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cpu_setup_prep_generic(self);
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: extintr.c,v 1.21 2006/05/03 17:47:06 garbled Exp $ */
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/* $NetBSD: extintr.c,v 1.22 2006/05/08 17:08:34 garbled Exp $ */
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/* $OpenBSD: isabus.c,v 1.12 1999/06/15 02:40:05 rahnds Exp $ */
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/*-
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@ -119,7 +119,7 @@ WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: extintr.c,v 1.21 2006/05/03 17:47:06 garbled Exp $");
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__KERNEL_RCSID(0, "$NetBSD: extintr.c,v 1.22 2006/05/08 17:08:34 garbled Exp $");
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#include "opt_openpic.h"
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#include "pci.h"
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@ -158,11 +158,9 @@ static void ext_intr_openpic(void);
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static void install_extint(void (*)(void));
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int imen = 0xffffffff;
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volatile int cpl, ipending, tickspending;
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int imask[NIPL];
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int intrtype[ICU_LEN], intrmask[ICU_LEN], intrlevel[ICU_LEN];
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struct intrhand *intrhand[ICU_LEN];
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unsigned intrcnt2[ICU_LEN];
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struct intrsource intrsources[ICU_LEN];
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static int
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fakeintr(void *arg)
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@ -171,108 +169,68 @@ fakeintr(void *arg)
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return 0;
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}
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#if 0
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static void ext_intr(void);
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/*
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* Process an interrupt from the ISA bus.
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* When we get here remember we have "delayed" ipl mask
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* settings from the spl<foo>() calls. Yes it's faster
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* to do it like this because SPL's are done so frequently
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* and interrupts are likely to *NOT* happen most of the
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* times the spl level is changed.
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*/
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static void
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ext_intr(void)
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{
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u_int8_t irq;
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int r_imen;
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int pcpl;
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struct intrhand *ih;
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/* what about enabling external interrupt in here? */
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pcpl = splhigh(); /* Turn off all */
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irq = isa_intr();
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intrcnt2[irq]++;
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r_imen = 1 << irq;
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if ((pcpl & r_imen) != 0) {
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ipending |= r_imen; /* Masked! Mark this as pending */
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imen |= r_imen;
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isa_intr_mask(imen);
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} else {
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ih = intrhand[irq];
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if (ih == NULL)
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printf("spurious interrupt %d\n", irq);
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while (ih) {
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(*ih->ih_fun)(ih->ih_arg);
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ih = ih->ih_next;
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}
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isa_intr_clr(irq);
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uvmexp.intrs++;
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intrcnt[irq]++;
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}
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splx(pcpl); /* Process pendings. */
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}
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#endif
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/*
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* Same as the above, but using the board's interrupt vector register.
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* ext_interrupts using the board's interrupt vector register.
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*/
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static void
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ext_intr_ivr(void)
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{
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u_int8_t irq;
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int r_imen;
|
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int pcpl;
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int r_imen, pcpl, msr;
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struct cpu_info *ci = curcpu();
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struct intrhand *ih;
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struct intrsource *is;
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/* what about enabling external interrupt in here? */
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pcpl = splhigh(); /* Turn off all */
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pcpl = ci->ci_cpl;
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msr = mfmsr();
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|
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irq = *((u_char *)prep_intr_reg + INTR_VECTOR_REG);
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intrcnt2[irq]++;
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is = &intrsources[irq];
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r_imen = 1 << irq;
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|
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if ((pcpl & r_imen) != 0) {
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ipending |= r_imen; /* Masked! Mark this as pending */
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ci->ci_ipending |= r_imen; /* Masked! Mark this as pending */
|
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imen |= r_imen;
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isa_intr_mask(imen);
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} else {
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ih = intrhand[irq];
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splraise(is->is_mask);
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mtmsr(msr | PSL_EE);
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KERNEL_LOCK(LK_CANRECURSE|LK_EXCLUSIVE);
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ih = is->is_hand;
|
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if (ih == NULL)
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printf("spurious interrupt %d\n", irq);
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while (ih) {
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(*ih->ih_fun)(ih->ih_arg);
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ih = ih->ih_next;
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}
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KERNEL_UNLOCK();
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mtmsr(msr);
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ci->ci_cpl = pcpl;
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|
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isa_intr_clr(irq);
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uvmexp.intrs++;
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intrcnt[irq]++;
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is->is_ev.ev_count++;
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}
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|
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mtmsr(msr | PSL_EE);
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splx(pcpl); /* Process pendings. */
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mtmsr(msr);
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}
|
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|
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#if defined(OPENPIC)
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static void
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ext_intr_openpic(void)
|
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{
|
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struct cpu_info *ci = curcpu();
|
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struct intrhand *ih;
|
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int r_imen;
|
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int pcpl;
|
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struct intrsource *is;
|
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int r_imen, pcpl, msr;
|
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u_int realirq;
|
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u_int8_t irq;
|
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|
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/* what about enabling external interrupt in here? */
|
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pcpl = splhigh(); /* Turn off all */
|
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msr = mfmsr();
|
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pcpl = ci->ci_cpl;
|
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|
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realirq = openpic_read_irq(0);
|
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while (realirq < OPENPIC_INTR_NUM) {
|
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@ -281,39 +239,46 @@ ext_intr_openpic(void)
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else
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irq = realirq + I8259_INTR_NUM;
|
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|
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intrcnt2[irq]++;
|
||||
is = &intrsources[irq];
|
||||
|
||||
r_imen = 1 << irq;
|
||||
|
||||
if ((pcpl & r_imen) != 0) {
|
||||
ipending |= r_imen;
|
||||
ci->ci_ipending |= r_imen;
|
||||
imen |= r_imen;
|
||||
if (realirq == 0)
|
||||
isa_intr_mask(imen);
|
||||
else
|
||||
openpic_disable_irq(realirq);
|
||||
} else {
|
||||
ih = intrhand[irq];
|
||||
splraise(is->is_mask);
|
||||
mtmsr(msr | PSL_EE);
|
||||
KERNEL_LOCK(LK_CANRECURSE|LK_EXCLUSIVE);
|
||||
ih = is->is_hand;
|
||||
if (ih == NULL)
|
||||
printf("spurious interrupt %d\n", irq);
|
||||
while (ih) {
|
||||
(*ih->ih_fun)(ih->ih_arg);
|
||||
ih = ih->ih_next;
|
||||
}
|
||||
KERNEL_UNLOCK();
|
||||
mtmsr(msr);
|
||||
ci->ci_cpl = pcpl;
|
||||
|
||||
if (realirq == 0)
|
||||
isa_intr_clr(irq);
|
||||
|
||||
uvmexp.intrs++;
|
||||
intrcnt[irq]++;
|
||||
is->is_ev.ev_count++;
|
||||
}
|
||||
|
||||
openpic_eoi(0);
|
||||
|
||||
realirq = openpic_read_irq(0);
|
||||
}
|
||||
|
||||
mtmsr(msr | PSL_EE);
|
||||
splx(pcpl); /* Process pendings. */
|
||||
mtmsr(msr);
|
||||
}
|
||||
#endif /* OPENPIC */
|
||||
|
||||
@ -321,6 +286,7 @@ void *
|
||||
intr_establish(int irq, int type, int level, int (*ih_fun)(void *), void *ih_arg)
|
||||
{
|
||||
struct intrhand **p, *q, *ih;
|
||||
struct intrsource *is;
|
||||
static struct intrhand fakehand = {fakeintr};
|
||||
|
||||
/* no point in sleeping unless someone can free memory. */
|
||||
@ -331,28 +297,42 @@ intr_establish(int irq, int type, int level, int (*ih_fun)(void *), void *ih_arg
|
||||
if (!LEGAL_IRQ(irq) || type == IST_NONE)
|
||||
panic("intr_establish: bogus irq or type");
|
||||
|
||||
switch (intrtype[irq]) {
|
||||
is = &intrsources[irq];
|
||||
is->is_hwirq = irq;
|
||||
|
||||
switch (is->is_type) {
|
||||
case IST_NONE:
|
||||
intrtype[irq] = type;
|
||||
is->is_type = type;
|
||||
break;
|
||||
case IST_LEVEL:
|
||||
case IST_EDGE:
|
||||
if (type == intrtype[irq])
|
||||
if (type == is->is_type)
|
||||
break;
|
||||
case IST_PULSE:
|
||||
if (type != IST_NONE)
|
||||
panic("intr_establish: can't share %s with %s irq %d",
|
||||
isa_intr_typename(intrtype[irq]),
|
||||
isa_intr_typename(is->is_type),
|
||||
isa_intr_typename(type), irq);
|
||||
break;
|
||||
}
|
||||
|
||||
if (is->is_hand == NULL) {
|
||||
snprintf(is->is_source, sizeof(is->is_source), "irq %d",
|
||||
is->is_hwirq);
|
||||
if (irq >= I8259_INTR_NUM)
|
||||
evcnt_attach_dynamic(&is->is_ev, EVCNT_TYPE_INTR, NULL,
|
||||
"openpic", is->is_source);
|
||||
else
|
||||
evcnt_attach_dynamic(&is->is_ev, EVCNT_TYPE_INTR, NULL,
|
||||
"8259", is->is_source);
|
||||
}
|
||||
|
||||
/*
|
||||
* Figure out where to put the handler.
|
||||
* This is O(N^2), but we want to preserve the order, and N is
|
||||
* generally small.
|
||||
*/
|
||||
for (p = &intrhand[irq]; (q = *p) != NULL; p = &q->ih_next)
|
||||
for (p = &is->is_hand; (q = *p) != NULL; p = &q->ih_next)
|
||||
continue;
|
||||
|
||||
/*
|
||||
@ -387,6 +367,7 @@ intr_disestablish(void *arg)
|
||||
{
|
||||
struct intrhand *ih = arg;
|
||||
int irq = ih->ih_irq;
|
||||
struct intrsource *is = &intrsources[irq];
|
||||
struct intrhand **p, *q;
|
||||
|
||||
if (!LEGAL_IRQ(irq))
|
||||
@ -396,7 +377,7 @@ intr_disestablish(void *arg)
|
||||
* Remove the handler from the chain.
|
||||
* This is O(n^2), too.
|
||||
*/
|
||||
for (p = &intrhand[irq]; (q = *p) != NULL && q != ih; p = &q->ih_next)
|
||||
for (p = &is->is_hand; (q = *p) != NULL && q != ih; p = &q->ih_next)
|
||||
continue;
|
||||
if (q == NULL)
|
||||
panic("intr_disestablish: handler not registered");
|
||||
@ -407,8 +388,10 @@ intr_disestablish(void *arg)
|
||||
|
||||
intr_calculatemasks();
|
||||
|
||||
if (intrhand[irq] == NULL)
|
||||
intrtype[irq] = IST_NONE;
|
||||
if (is->is_hand == NULL) {
|
||||
is->is_type = IST_NONE;
|
||||
evcnt_detach(&is->is_ev);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
@ -421,21 +404,22 @@ static void
|
||||
intr_calculatemasks(void)
|
||||
{
|
||||
int irq, level;
|
||||
struct intrsource *is;
|
||||
struct intrhand *q;
|
||||
|
||||
/* First, figure out which levels each IRQ uses. */
|
||||
for (irq = 0; irq < ICU_LEN; irq++) {
|
||||
for (irq = 0, is = intrsources; irq < ICU_LEN; irq++, is++) {
|
||||
register int levels = 0;
|
||||
for (q = intrhand[irq]; q; q = q->ih_next)
|
||||
for (q = is->is_hand; q; q = q->ih_next)
|
||||
levels |= 1 << q->ih_level;
|
||||
intrlevel[irq] = levels;
|
||||
is->is_level = levels;
|
||||
}
|
||||
|
||||
/* Then figure out which IRQs use each level. */
|
||||
for (level = 0; level < NIPL; level++) {
|
||||
register int irqs = 0;
|
||||
for (irq = 0; irq < ICU_LEN; irq++)
|
||||
if (intrlevel[irq] & (1 << level))
|
||||
for (irq = 0, is = intrsources; irq < ICU_LEN; irq++, is++)
|
||||
if (is->is_level & (1 << level))
|
||||
irqs |= 1 << irq;
|
||||
imask[level] = irqs;
|
||||
}
|
||||
@ -491,17 +475,18 @@ intr_calculatemasks(void)
|
||||
imask[IPL_SERIAL] |= imask[IPL_HIGH];
|
||||
|
||||
/* And eventually calculate the complete masks. */
|
||||
for (irq = 0; irq < ICU_LEN; irq++) {
|
||||
for (irq = 0, is = intrsources; irq < ICU_LEN; irq++, is++) {
|
||||
register int irqs = 1 << irq;
|
||||
for (q = intrhand[irq]; q; q = q->ih_next)
|
||||
for (q = is->is_hand; q; q = q->ih_next)
|
||||
irqs |= imask[q->ih_level];
|
||||
intrmask[irq] = irqs;
|
||||
is->is_mask = irqs;
|
||||
}
|
||||
|
||||
{
|
||||
register int irqs = 0;
|
||||
for (irq = 0; irq < I8259_INTR_NUM; irq++)
|
||||
if (intrhand[irq])
|
||||
for (irq = 0, is = intrsources; irq < I8259_INTR_NUM;
|
||||
irq++, is++)
|
||||
if (is->is_hand)
|
||||
irqs |= 1 << irq;
|
||||
if (irqs >= 0x100) /* any IRQs >= 8 in use */
|
||||
irqs |= 1 << IRQ_SLAVE;
|
||||
@ -511,10 +496,11 @@ intr_calculatemasks(void)
|
||||
#if defined(OPENPIC)
|
||||
if (openpic_base) {
|
||||
openpic_enable_irq(0, IST_LEVEL);
|
||||
for (irq = I8259_INTR_NUM + 1; irq < ICU_LEN; irq++) {
|
||||
if (intrhand[irq]) {
|
||||
for (irq = I8259_INTR_NUM + 1, is = &intrsources[irq];
|
||||
irq < ICU_LEN; irq++, is++) {
|
||||
if (is->is_hand) {
|
||||
openpic_enable_irq(irq - I8259_INTR_NUM,
|
||||
intrtype[irq]);
|
||||
is->is_type);
|
||||
} else {
|
||||
openpic_disable_irq(irq);
|
||||
}
|
||||
@ -527,31 +513,30 @@ intr_calculatemasks(void)
|
||||
void
|
||||
do_pending_int(void)
|
||||
{
|
||||
struct cpu_info * const ci = curcpu();
|
||||
struct intrhand *ih;
|
||||
int irq;
|
||||
int pcpl;
|
||||
int hwpend;
|
||||
int emsr, dmsr;
|
||||
static int processing;
|
||||
struct intrsource *is;
|
||||
int irq, pcpl, hwpend, emsr, dmsr;
|
||||
|
||||
if (processing)
|
||||
if (ci->ci_iactive)
|
||||
return;
|
||||
|
||||
processing = 1;
|
||||
ci->ci_iactive = 1;
|
||||
__asm volatile("mfmsr %0" : "=r"(emsr));
|
||||
dmsr = emsr & ~PSL_EE;
|
||||
__asm volatile("mtmsr %0" :: "r"(dmsr));
|
||||
|
||||
pcpl = splhigh(); /* Turn off all */
|
||||
pcpl = ci->ci_cpl; /* Turn off all */
|
||||
again:
|
||||
|
||||
hwpend = ipending & ~pcpl; /* Do now unmasked pendings */
|
||||
hwpend = ci->ci_ipending & ~pcpl; /* Do now unmasked pendings */
|
||||
imen &= ~hwpend;
|
||||
hwpend &= ~SINT_MASK;
|
||||
while (hwpend) {
|
||||
irq = ffs(hwpend) - 1;
|
||||
is = &intrsources[irq];
|
||||
hwpend &= ~(1L << irq);
|
||||
ih = intrhand[irq];
|
||||
ih = is->is_hand;
|
||||
while (ih) {
|
||||
(*ih->ih_fun)(ih->ih_arg);
|
||||
ih = ih->ih_next;
|
||||
@ -559,52 +544,56 @@ again:
|
||||
|
||||
#if defined(OPENPIC)
|
||||
if (irq >= I8259_INTR_NUM)
|
||||
openpic_enable_irq(irq - I8259_INTR_NUM, intrtype[irq]);
|
||||
openpic_enable_irq(irq - I8259_INTR_NUM, is->is_type);
|
||||
else
|
||||
#endif /* OPENPIC */
|
||||
isa_intr_clr(irq);
|
||||
|
||||
uvmexp.intrs++;
|
||||
intrcnt[irq]++;
|
||||
is->is_ev.ev_count++;
|
||||
}
|
||||
if ((ipending & ~pcpl) & SINT_CLOCK) {
|
||||
ipending &= ~SINT_CLOCK;
|
||||
if ((ci->ci_ipending & ~pcpl) & SINT_CLOCK) {
|
||||
ci->ci_ipending &= ~SINT_CLOCK;
|
||||
splsoftclock();
|
||||
mtmsr(emsr);
|
||||
KERNEL_LOCK(LK_CANRECURSE|LK_EXCLUSIVE);
|
||||
softintr__run(IPL_SOFTCLOCK);
|
||||
KERNEL_UNLOCK();
|
||||
mtmsr(dmsr);
|
||||
ci->ci_cpl = pcpl;
|
||||
ci->ci_ev_softclock.ev_count++;
|
||||
goto again;
|
||||
}
|
||||
if ((ipending & ~pcpl) & SINT_NET) {
|
||||
ipending &= ~SINT_NET;
|
||||
if ((ci->ci_ipending & ~pcpl) & SINT_NET) {
|
||||
ci->ci_ipending &= ~SINT_NET;
|
||||
splsoftnet();
|
||||
mtmsr(emsr);
|
||||
KERNEL_LOCK(LK_CANRECURSE|LK_EXCLUSIVE);
|
||||
softintr__run(IPL_SOFTNET);
|
||||
KERNEL_UNLOCK();
|
||||
mtmsr(dmsr);
|
||||
ci->ci_cpl = pcpl;
|
||||
ci->ci_ev_softnet.ev_count++;
|
||||
goto again;
|
||||
}
|
||||
if ((ipending & ~pcpl) & SINT_SERIAL) {
|
||||
ipending &= ~SINT_SERIAL;
|
||||
if ((ci->ci_ipending & ~pcpl) & SINT_SERIAL) {
|
||||
ci->ci_ipending &= ~SINT_SERIAL;
|
||||
splsoftserial();
|
||||
mtmsr(emsr);
|
||||
KERNEL_LOCK(LK_CANRECURSE|LK_EXCLUSIVE);
|
||||
softintr__run(IPL_SOFTSERIAL);
|
||||
KERNEL_UNLOCK();
|
||||
mtmsr(dmsr);
|
||||
ci->ci_cpl = pcpl;
|
||||
ci->ci_ev_softserial.ev_count++;
|
||||
goto again;
|
||||
}
|
||||
|
||||
ipending &= pcpl;
|
||||
cpl = pcpl; /* Don't use splx... we are here already! */
|
||||
|
||||
ci->ci_ipending &= pcpl;
|
||||
ci->ci_cpl = pcpl; /* Don't use splx... we are here already! */
|
||||
isa_intr_mask(imen);
|
||||
|
||||
__asm volatile("mtmsr %0" :: "r"(emsr));
|
||||
processing = 0;
|
||||
ci->ci_iactive = 0;
|
||||
mtmsr(emsr);
|
||||
}
|
||||
|
||||
static void
|
||||
@ -719,3 +708,50 @@ init_intr(void)
|
||||
#endif
|
||||
install_extint(ext_intr_ivr);
|
||||
}
|
||||
|
||||
/*
|
||||
* Reorder protection in the following inline functions is
|
||||
* achieved with the "eieio" instruction which the assembler
|
||||
* seems to detect and then doesn't move instructions past....
|
||||
*/
|
||||
|
||||
int
|
||||
splraise(int newcpl)
|
||||
{
|
||||
struct cpu_info *ci = curcpu();
|
||||
int oldcpl;
|
||||
|
||||
__asm volatile("sync; eieio\n"); /* don't reorder.... */
|
||||
oldcpl = ci->ci_cpl;
|
||||
ci->ci_cpl = oldcpl | newcpl;
|
||||
__asm volatile("sync; eieio\n"); /* reorder protect */
|
||||
return(oldcpl);
|
||||
}
|
||||
|
||||
int
|
||||
spllower(int newcpl)
|
||||
{
|
||||
struct cpu_info *ci = curcpu();
|
||||
int ocpl;
|
||||
|
||||
__asm volatile("sync; eieio\n"); /* reorder protect */
|
||||
ocpl = ci->ci_cpl;
|
||||
ci->ci_cpl = newcpl;
|
||||
if(ci->ci_ipending & ~newcpl)
|
||||
do_pending_int();
|
||||
__asm volatile("sync; eieio\n"); /* reorder protect */
|
||||
return ocpl;
|
||||
}
|
||||
|
||||
/* Following code should be implemented with lwarx/stwcx to avoid
|
||||
* the disable/enable. i need to read the manual once more.... */
|
||||
void
|
||||
softintr(int pending)
|
||||
{
|
||||
int msrsave;
|
||||
|
||||
msrsave = mfmsr();
|
||||
mtmsr(msrsave & ~PSL_EE);
|
||||
curcpu()->ci_ipending |= pending;
|
||||
mtmsr(msrsave);
|
||||
}
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: locore.S,v 1.8 2005/12/11 12:18:48 christos Exp $ */
|
||||
/* $NetBSD: locore.S,v 1.9 2006/05/08 17:08:34 garbled Exp $ */
|
||||
/* $OpenBSD: locore.S,v 1.4 1997/01/26 09:06:38 rahnds Exp $ */
|
||||
|
||||
/*
|
||||
@ -80,22 +80,6 @@ GLOBAL(endsym)
|
||||
GLOBAL(proc0paddr)
|
||||
.long 0 /* proc0 p_addr */
|
||||
|
||||
GLOBAL(intrnames)
|
||||
.asciz "clock", "irq1", "irq2", "irq3"
|
||||
.asciz "irq4", "irq5", "irq6", "irq7"
|
||||
.asciz "irq8", "irq9", "irq10", "irq11"
|
||||
.asciz "irq12", "irq13", "irq14", "irq15"
|
||||
.asciz "irq16", "irq17", "irq18", "irq19"
|
||||
.asciz "irq20", "irq21", "irq22", "irq23"
|
||||
.asciz "irq24", "irq25", "irq26", "irq27"
|
||||
.asciz "irq28", "softnet", "softclock", "softserial"
|
||||
GLOBAL(eintrnames)
|
||||
.align 4
|
||||
GLOBAL(intrcnt)
|
||||
.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
|
||||
.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
|
||||
GLOBAL(eintrcnt)
|
||||
|
||||
/*
|
||||
* This symbol is here for the benefit of kvm_mkdb, and is supposed to
|
||||
* mark the start of kernel text.
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: machdep.c,v 1.59 2006/05/03 17:47:06 garbled Exp $ */
|
||||
/* $NetBSD: machdep.c,v 1.60 2006/05/08 17:08:34 garbled Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (C) 1995, 1996 Wolfgang Solfrank.
|
||||
@ -32,7 +32,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.59 2006/05/03 17:47:06 garbled Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.60 2006/05/08 17:08:34 garbled Exp $");
|
||||
|
||||
#include "opt_compat_netbsd.h"
|
||||
#include "opt_ddb.h"
|
||||
@ -384,15 +384,15 @@ halt_sys:
|
||||
* splx() differing in that it returns the previous priority level.
|
||||
*/
|
||||
int
|
||||
lcsplx(ipl)
|
||||
int ipl;
|
||||
lcsplx(int ipl)
|
||||
{
|
||||
int oldcpl;
|
||||
struct cpu_info *ci = curcpu();
|
||||
|
||||
__asm volatile("sync; eieio\n"); /* reorder protect */
|
||||
oldcpl = cpl;
|
||||
cpl = ipl;
|
||||
if (ipending & ~ipl)
|
||||
oldcpl = ci->ci_cpl;
|
||||
ci->ci_cpl = ipl;
|
||||
if (ci->ci_ipending & ~ipl)
|
||||
do_pending_int();
|
||||
__asm volatile("sync; eieio\n"); /* reorder protect */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user