read/write-allocate line allocation policy.
On the i80321, this improves nearly every lmbench benchmark, dramatically
so the ones that are sensitive to memory bandwidth (100-300% improvement
for these).
cache, as well. The mini-data cache is 2-way, so src and dst won't
clobber each other, and the smallness of the cache doesn't matter,
since we access each page once sequentially.
While we still have to do the initial clean of the source page, this
saves another 4K of main D$ pollution, and also means we don't have
to do 2 cache passes after the copy is complete (i.e. we can skip the
invalidation of the source page in the main cache, since it's no longer
there).
vs. XScale. Use the mini-data cache for the destination on XScale,
thus saving tossing out 4K of possible-useful data from the main
data cache each time.
This significantly improves every test in lmbench.
and pte_l2_s_cache_mode. The cache-meaningful bits are different
for these descriptor types on some processor models.
* Add pte_*_cache_mask, corresponding to each above, which has a mask
of the cache-meangful bits, and define those for generic and XScale
MMU classes. Note, the L2_S_CACHE_MASK_xscale definition requires
use of the Extended Small Page L2 descriptor (the "X" bit overlaps
with AP bits otherwise).
the data transfer. This is mandatory for data out commands (although none are
used for now), and not forbiddend for data in commands. Also record if we
did transfers any data.
May solve kern/16159 by making the probe more robust in face of fake identify.
L1_C_PROTO_xscale; while they are supposed to be set to 1 on generic
ARM MMUs (according to the SA-110 and ARM920T manuals), they are listed
as "should be zero" in the i80200 manual.
1. Generic (compatible with ARM6)
1. XScale (can be used as generic, but also has certainly nifty extensions).
Define abstract PTE bit defintions for each MMU class. If only one MMU
class is configured into the kernel (based on CPU_* options), then we
get the constants for that MMU class. Otherwise we indirect through
varaibles set up via set_cpufuncs().
XXX The XScale bits are currently the same as the generic bits. Baby steps.
after setting up the prom-based console. If more than one cpu class
is enabled, the wbflush() handler (needed indirectly by com.c) won't
be set up.
- Purge some old pmax mcclock-based code.
- Remove a '#if 1/#endif' pair.
- Use the CPU count register for more accurate microtime (from
sbmips) and delay (based on an evbmips delay function) functions.
- Schedule the next hardclock interrupt more accurately (from
an sgimips patch by Rafal Boni). Clock drift on one board is
now ~7ppm instead of ~330ppm.
- Purge old pmax-based mcclock code.
- Correctly round off some clock-derived variable calculations.
XXX: Some of this code should be migrated to sys/arch/mips.
for the same purpose (ignoring invalid interrupts).
For cards that are not able to stop all interrupts (or we don't know a way
to do that in software, at least) run the clearirq callback even when
ignoring an interrupt because we are not enabled. Otherwise the card would
stop interrupting.
Reserve a driver specific callout handle and an int value in the generic
isic_softc to allow card drivers to implement fancy blinkenlights.
It improves playing/recording quality greatly
and it was almost done by Yosuke Sugahara <penta@fuchu.or.jp>.
Thanks a lot!
Add support of slinear8, slinear16_le, slinear16_be.
do not have ARP configured.
This can be caused by configurations including bridge, ppppoe or vlan but
no ethernet interfaces - which does not make sense. We should add a way
to config(8) to issue this kind of warnings.
pcmcia cards. Now that pcmcia attachements properly handle the activate
callback, this is no longer needed (and is suspect to cause completely
unrelated problems.)
count them when reading the NIC counters - it doubles the count. Read the
NIC counters to prevent counter overflow interrupts, but don't add them to
the interface counters. Don't bother reading the upper counts because they
are just latched when reading the totals.
Fixes final part of PR#11549.
thorpej