1. ABLE sets the l1pt to use domain 3 for it's entries (no idea why) so to
cover all bases when setting the domain before the change to the new L1pt
become a client of all domains.
2. It seems that we setup the kernel entries without any access permission.
(note not sure that this isn't a bug) And rely on the control bits
containing either ROM or SYST enable. which allows access to pages without
access permissions set. We actually enable SYST when we do the full detect
of the CPU, but we don't detect the CPU till after the L1pt switch, which
we never make it past. Fix this by explicitly enabling the SYST bit in the
control register. rather than relying on the firmware to have dont the right
thing.
esiop has been tested enouth now.
esiop not added to INSTALL kernels because of possible space constraint.
siop should be able to drive all adapters supported by esiop.
Also in the ARM32_PMAP_NEW case, reclaim the USPACE-bytes of wasted space
at the top of the user address that hasn't been needed for a very very
long time.
cd ${KERNSRCDIR}/${KERNARCHDIR}/compile && ${PRINTOBJDIR}
This is far simpler than the previous system, and more robust with
objdirs built via BSDOBJDIR.
The previous method of finding KERNOBJDIR when using BSDOBJDIR by
referencing _SRC_TOP_OBJ_ from another directory was extremely
fragile due to the depth first tree walk by <bsd.subdir.mk>, and
the caching of _SRC_TOP_OBJ_ (with MAKEOVERRIDES) which would be
empty on the *first* pass to create fresh objdirs.
This change requires adding sys/arch/*/compile/Makefile to create
the objdir in that directory, and descending into arch/*/compile
from arch/*/Makefile. Remove the now-unnecessary .keep_me files
whilst here.
Per lengthy discussion with Andrew Brown.
This is based upon Jason's work on xscale.
Most of the interrupt handling code is now written in C using an asm stub to
call into the C code.
spl* now only updates a software mask, and does not update the hardware,
this should be much faster.
The new code works well on cats, it's untested on netwinder, but should work.
The code implements generic soft interrupts.
More work is still required to bring the isa interrupt handling code upto
scratch currently all isa interrupts are handled at IPL_BIO on the footbridge.
This may cause isa interrupts to be handled later than they should be.
I plan to fix this in the near future.
joins other machdep files)
Saves maintaining multiple copies of the same thing, the only differences
were:
IRQ line used on the footbridge (made that a define in include/isa_machdep.h)
name of a dma_ranges variable contained arch name, so just made it generic.
