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@ -1,597 +0,0 @@
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/* $NetBSD: isa_machdep.c,v 1.6 2002/10/09 00:33:39 thorpej Exp $ */
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/*-
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* Copyright (c) 1996-1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Mark Brinicombe, Charles M. Hannum and by Jason R. Thorpe of the
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* Numerical Aerospace Simulation Facility, NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*-
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)isa.c 7.2 (Berkeley) 5/13/91
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*/
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#include "opt_irqstats.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/syslog.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <sys/proc.h>
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#define _ARM32_BUS_DMA_PRIVATE
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/pio.h>
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#include <machine/bootconfig.h>
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#include <dev/isa/isareg.h>
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#include <dev/isa/isavar.h>
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#include <dev/isa/isadmareg.h>
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#include <dev/isa/isadmavar.h>
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#include <arm/footbridge/isa/icu.h>
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#include <arm/footbridge/dc21285reg.h>
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#include <arm/footbridge/dc21285mem.h>
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#include <uvm/uvm_extern.h>
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#include "isadma.h"
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struct arm32_isa_chipset isa_chipset_tag;
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void isa_strayintr __P((int));
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void intr_calculatemasks __P((void));
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int fakeintr __P((void *));
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int isa_irqdispatch __P((void *arg));
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u_int imask[IPL_LEVELS];
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unsigned imen;
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#ifdef IRQSTATS
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u_int isa_intr_count[ICU_LEN];
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#endif /* IRQSTATS */
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#define AUTO_EOI_1
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#define AUTO_EOI_2
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/*
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* Fill in default interrupt table (in case of spuruious interrupt
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* during configuration of kernel, setup interrupt control unit
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*/
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static void
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isa_icu_init(void)
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{
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/* initialize 8259's */
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outb(IO_ICU1, 0x11); /* reset; program device, four bytes */
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outb(IO_ICU1+1, ICU_OFFSET); /* starting at this vector index */
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outb(IO_ICU1+1, 1 << IRQ_SLAVE); /* slave on line 2 */
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#ifdef AUTO_EOI_1
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outb(IO_ICU1+1, 2 | 1); /* auto EOI, 8086 mode */
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#else
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outb(IO_ICU1+1, 1); /* 8086 mode */
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#endif
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outb(IO_ICU1+1, 0xff); /* leave interrupts masked */
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outb(IO_ICU1, 0x68); /* special mask mode (if available) */
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outb(IO_ICU1, 0x0a); /* Read IRR by default. */
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#ifdef REORDER_IRQ
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outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */
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#endif
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outb(IO_ICU2, 0x11); /* reset; program device, four bytes */
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outb(IO_ICU2+1, ICU_OFFSET+8); /* staring at this vector index */
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outb(IO_ICU2+1, IRQ_SLAVE);
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#ifdef AUTO_EOI_2
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outb(IO_ICU2+1, 2 | 1); /* auto EOI, 8086 mode */
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#else
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outb(IO_ICU2+1, 1); /* 8086 mode */
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#endif
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outb(IO_ICU2+1, 0xff); /* leave interrupts masked */
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outb(IO_ICU2, 0x68); /* special mask mode (if available) */
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outb(IO_ICU2, 0x0a); /* Read IRR by default. */
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}
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/*
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* Caught a stray interrupt, notify
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*/
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void
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isa_strayintr(irq)
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int irq;
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{
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static u_long strays;
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/*
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* Stray interrupts on irq 7 occur when an interrupt line is raised
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* and then lowered before the CPU acknowledges it. This generally
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* means either the device is screwed or something is cli'ing too
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* long and it's timing out.
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*/
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if (++strays <= 5)
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log(LOG_ERR, "stray interrupt %d%s\n", irq,
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strays >= 5 ? "; stopped logging" : "");
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}
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int intrtype[ICU_LEN], intrmask[ICU_LEN], intrlevel[ICU_LEN];
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struct irqhandler *intrhand[ICU_LEN];
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/*
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* Recalculate the interrupt masks from scratch.
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* We could code special registry and deregistry versions of this function that
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* would be faster, but the code would be nastier, and we don't expect this to
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* happen very much anyway.
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*/
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void
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intr_calculatemasks()
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{
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int irq, level;
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struct irqhandler *q;
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/* First, figure out which levels each IRQ uses. */
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for (irq = 0; irq < ICU_LEN; irq++) {
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int levels = 0;
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for (q = intrhand[irq]; q; q = q->ih_next)
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levels |= 1 << q->ih_level;
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intrlevel[irq] = levels;
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}
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/* Then figure out which IRQs use each level. */
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for (level = 0; level < IPL_LEVELS; level++) {
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int irqs = 0;
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for (irq = 0; irq < ICU_LEN; irq++)
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if (intrlevel[irq] & (1 << level))
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irqs |= 1 << irq;
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imask[level] = irqs;
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}
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/*
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* IPL_NONE is used for hardware interrupts that are never blocked,
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* and do not block anything else.
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*/
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imask[IPL_NONE] = 0;
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/*
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* Enforce a hierarchy that gives slow devices a better chance at not
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* dropping data.
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*/
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imask[IPL_BIO] |= imask[IPL_NONE];
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imask[IPL_NET] |= imask[IPL_BIO];
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imask[IPL_TTY] |= imask[IPL_NET];
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/*
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* There are tty, network and disk drivers that use free() at interrupt
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* time, so imp > (tty | net | bio).
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*/
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imask[IPL_IMP] |= imask[IPL_TTY];
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imask[IPL_AUDIO] |= imask[IPL_IMP];
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/*
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* Since run queues may be manipulated by both the statclock and tty,
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* network, and disk drivers, clock > imp.
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*/
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imask[IPL_CLOCK] |= imask[IPL_AUDIO];
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imask[IPL_CLOCK] |= imask[IPL_IMP];
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/*
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* IPL_HIGH must block everything that can manipulate a run queue.
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*/
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imask[IPL_HIGH] |= imask[IPL_CLOCK];
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/*
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* We need serial drivers to run at the absolute highest priority to
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* avoid overruns, so serial > high.
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*/
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imask[IPL_SERIAL] |= imask[IPL_HIGH];
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/* And eventually calculate the complete masks. */
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for (irq = 0; irq < ICU_LEN; irq++) {
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int irqs = 1 << irq;
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for (q = intrhand[irq]; q; q = q->ih_next)
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irqs |= imask[q->ih_level];
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intrmask[irq] = irqs;
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}
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/* Lastly, determine which IRQs are actually in use. */
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{
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int irqs = 0;
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for (irq = 0; irq < ICU_LEN; irq++)
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if (intrhand[irq])
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irqs |= 1 << irq;
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if (irqs >= 0x100) /* any IRQs >= 8 in use */
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irqs |= 1 << IRQ_SLAVE;
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imen = ~irqs;
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SET_ICUS();
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}
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#if 0
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printf("type\tmask\tlevel\thand\n");
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for (irq = 0; irq < ICU_LEN; irq++) {
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printf("%x\t%04x\t%x\t%p\n", intrtype[irq], intrmask[irq],
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intrlevel[irq], intrhand[irq]);
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}
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for (level = 0; level < IPL_LEVELS; ++level)
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printf("%d: %08x\n", level, imask[level]);
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#endif
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}
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int
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fakeintr(arg)
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void *arg;
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{
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return 0;
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}
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#define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != 2)
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int
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isa_intr_alloc(ic, mask, type, irq)
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isa_chipset_tag_t ic;
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int mask;
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int type;
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int *irq;
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{
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int i, tmp, bestirq, count;
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struct irqhandler **p, *q;
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if (type == IST_NONE)
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panic("intr_alloc: bogus type");
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bestirq = -1;
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count = -1;
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/* some interrupts should never be dynamically allocated */
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mask &= 0xdef8;
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/*
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* XXX some interrupts will be used later (6 for fdc, 12 for pms).
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* the right answer is to do "breadth-first" searching of devices.
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*/
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mask &= 0xefbf;
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for (i = 0; i < ICU_LEN; i++) {
|
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|
|
|
if (LEGAL_IRQ(i) == 0 || (mask & (1<<i)) == 0)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
switch(intrtype[i]) {
|
|
|
|
|
case IST_NONE:
|
|
|
|
|
/*
|
|
|
|
|
* if nothing's using the irq, just return it
|
|
|
|
|
*/
|
|
|
|
|
*irq = i;
|
|
|
|
|
return (0);
|
|
|
|
|
|
|
|
|
|
case IST_EDGE:
|
|
|
|
|
case IST_LEVEL:
|
|
|
|
|
if (type != intrtype[i])
|
|
|
|
|
continue;
|
|
|
|
|
/*
|
|
|
|
|
* if the irq is shareable, count the number of other
|
|
|
|
|
* handlers, and if it's smaller than the last irq like
|
|
|
|
|
* this, remember it
|
|
|
|
|
*
|
|
|
|
|
* XXX We should probably also consider the
|
|
|
|
|
* interrupt level and stick IPL_TTY with other
|
|
|
|
|
* IPL_TTY, etc.
|
|
|
|
|
*/
|
|
|
|
|
for (p = &intrhand[i], tmp = 0; (q = *p) != NULL;
|
|
|
|
|
p = &q->ih_next, tmp++)
|
|
|
|
|
;
|
|
|
|
|
if ((bestirq == -1) || (count > tmp)) {
|
|
|
|
|
bestirq = i;
|
|
|
|
|
count = tmp;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case IST_PULSE:
|
|
|
|
|
/* this just isn't shareable */
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (bestirq == -1)
|
|
|
|
|
return (1);
|
|
|
|
|
|
|
|
|
|
*irq = bestirq;
|
|
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
const struct evcnt *
|
|
|
|
|
isa_intr_evcnt(isa_chipset_tag_t ic, int irq)
|
|
|
|
|
{
|
|
|
|
|
|
|
|
|
|
/* XXX for now, no evcnt parent reported */
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Set up an interrupt handler to start being called.
|
|
|
|
|
* XXX PRONE TO RACE CONDITIONS, UGLY, 'INTERESTING' INSERTION ALGORITHM.
|
|
|
|
|
*/
|
|
|
|
|
void *
|
|
|
|
|
isa_intr_establish(ic, irq, type, level, ih_fun, ih_arg)
|
|
|
|
|
isa_chipset_tag_t ic;
|
|
|
|
|
int irq;
|
|
|
|
|
int type;
|
|
|
|
|
int level;
|
|
|
|
|
int (*ih_fun) __P((void *));
|
|
|
|
|
void *ih_arg;
|
|
|
|
|
{
|
|
|
|
|
struct irqhandler **p, *q, *ih;
|
|
|
|
|
static struct irqhandler fakehand = {fakeintr};
|
|
|
|
|
|
|
|
|
|
/* printf("isa_intr_establish(%d, %d, %d)\n", irq, type, level);*/
|
|
|
|
|
|
|
|
|
|
/* no point in sleeping unless someone can free memory. */
|
|
|
|
|
ih = malloc(sizeof *ih, M_DEVBUF, cold ? M_NOWAIT : M_WAITOK);
|
|
|
|
|
if (ih == NULL)
|
|
|
|
|
panic("isa_intr_establish: can't malloc handler info");
|
|
|
|
|
|
|
|
|
|
if (!LEGAL_IRQ(irq) || type == IST_NONE)
|
|
|
|
|
panic("intr_establish: bogus irq or type");
|
|
|
|
|
|
|
|
|
|
switch (intrtype[irq]) {
|
|
|
|
|
case IST_NONE:
|
|
|
|
|
intrtype[irq] = type;
|
|
|
|
|
/* printf("Setting irq %d to type %d - ", irq, type);*/
|
|
|
|
|
if (irq < 8) {
|
|
|
|
|
outb(0x4d0, (inb(0x4d0) & ~(1 << irq))
|
|
|
|
|
| ((type == IST_LEVEL) ? (1 << irq) : 0));
|
|
|
|
|
/* printf("%02x\n", inb(0x4d0));*/
|
|
|
|
|
} else {
|
|
|
|
|
outb(0x4d1, (inb(0x4d1) & ~(1 << irq))
|
|
|
|
|
| ((type == IST_LEVEL) ? (1 << irq) : 0));
|
|
|
|
|
/* printf("%02x\n", inb(0x4d1));*/
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case IST_EDGE:
|
|
|
|
|
case IST_LEVEL:
|
|
|
|
|
if (type == intrtype[irq])
|
|
|
|
|
break;
|
|
|
|
|
case IST_PULSE:
|
|
|
|
|
if (type != IST_NONE)
|
|
|
|
|
panic("intr_establish: can't share %s with %s",
|
|
|
|
|
isa_intr_typename(intrtype[irq]),
|
|
|
|
|
isa_intr_typename(type));
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Figure out where to put the handler.
|
|
|
|
|
* This is O(N^2), but we want to preserve the order, and N is
|
|
|
|
|
* generally small.
|
|
|
|
|
*/
|
|
|
|
|
for (p = &intrhand[irq]; (q = *p) != NULL; p = &q->ih_next)
|
|
|
|
|
;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Actually install a fake handler momentarily, since we might be doing
|
|
|
|
|
* this with interrupts enabled and don't want the real routine called
|
|
|
|
|
* until masking is set up.
|
|
|
|
|
*/
|
|
|
|
|
fakehand.ih_level = level;
|
|
|
|
|
*p = &fakehand;
|
|
|
|
|
|
|
|
|
|
intr_calculatemasks();
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Poke the real handler in now.
|
|
|
|
|
*/
|
|
|
|
|
ih->ih_func = ih_fun;
|
|
|
|
|
ih->ih_arg = ih_arg;
|
|
|
|
|
/* ih->ih_count = 0;*/
|
|
|
|
|
ih->ih_next = NULL;
|
|
|
|
|
ih->ih_level = level;
|
|
|
|
|
ih->ih_num = irq;
|
|
|
|
|
*p = ih;
|
|
|
|
|
|
|
|
|
|
return (ih);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Deregister an interrupt handler.
|
|
|
|
|
*/
|
|
|
|
|
void
|
|
|
|
|
isa_intr_disestablish(ic, arg)
|
|
|
|
|
isa_chipset_tag_t ic;
|
|
|
|
|
void *arg;
|
|
|
|
|
{
|
|
|
|
|
struct irqhandler *ih = arg;
|
|
|
|
|
int irq = ih->ih_num;
|
|
|
|
|
struct irqhandler **p, *q;
|
|
|
|
|
|
|
|
|
|
if (!LEGAL_IRQ(irq))
|
|
|
|
|
panic("intr_disestablish: bogus irq");
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Remove the handler from the chain.
|
|
|
|
|
* This is O(n^2), too.
|
|
|
|
|
*/
|
|
|
|
|
for (p = &intrhand[irq]; (q = *p) != NULL && q != ih; p = &q->ih_next)
|
|
|
|
|
;
|
|
|
|
|
if (q)
|
|
|
|
|
*p = q->ih_next;
|
|
|
|
|
else
|
|
|
|
|
panic("intr_disestablish: handler not registered");
|
|
|
|
|
free(ih, M_DEVBUF);
|
|
|
|
|
|
|
|
|
|
intr_calculatemasks();
|
|
|
|
|
|
|
|
|
|
if (intrhand[irq] == NULL)
|
|
|
|
|
intrtype[irq] = IST_NONE;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* isa_intr_init()
|
|
|
|
|
*
|
|
|
|
|
* Initialise the ISA ICU and attach an ISA interrupt handler to the
|
|
|
|
|
* ISA interrupt line on the footbridge.
|
|
|
|
|
*/
|
|
|
|
|
void
|
|
|
|
|
isa_intr_init(void)
|
|
|
|
|
{
|
|
|
|
|
static void *isa_ih;
|
|
|
|
|
|
|
|
|
|
isa_icu_init();
|
|
|
|
|
isa_ih = intr_claim(IRQ_IN_L3, IPL_BIO, "isabus",
|
|
|
|
|
isa_irqdispatch, NULL);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Static array of ISA DMA segments. We only have one on CATS */
|
|
|
|
|
#if NISADMA > 0
|
|
|
|
|
struct arm32_dma_range netwinder_isa_dma_ranges[1];
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
isa_netwinder_init(iobase, membase)
|
|
|
|
|
u_int iobase, membase;
|
|
|
|
|
{
|
|
|
|
|
#if NISADMA > 0
|
|
|
|
|
extern struct arm32_dma_range *footbridge_isa_dma_ranges;
|
|
|
|
|
extern int footbridge_isa_dma_nranges;
|
|
|
|
|
|
|
|
|
|
netwinder_isa_dma_ranges[0].dr_sysbase = bootconfig.dram[0].address;
|
|
|
|
|
netwinder_isa_dma_ranges[0].dr_busbase = bootconfig.dram[0].address;
|
|
|
|
|
netwinder_isa_dma_ranges[0].dr_len = (16 * 1024 * 1024);
|
|
|
|
|
|
|
|
|
|
footbridge_isa_dma_ranges = netwinder_isa_dma_ranges;
|
|
|
|
|
footbridge_isa_dma_nranges = 1;
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
isa_io_init(iobase, membase);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
isa_attach_hook(parent, self, iba)
|
|
|
|
|
struct device *parent, *self;
|
|
|
|
|
struct isabus_attach_args *iba;
|
|
|
|
|
{
|
|
|
|
|
/*
|
|
|
|
|
* Since we can only have one ISA bus, we just use a single
|
|
|
|
|
* statically allocated ISA chipset structure. Pass it up
|
|
|
|
|
* now.
|
|
|
|
|
*/
|
|
|
|
|
iba->iba_ic = &isa_chipset_tag;
|
|
|
|
|
#if NISADMA > 0
|
|
|
|
|
isa_dma_init();
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int
|
|
|
|
|
isa_irqdispatch(arg)
|
|
|
|
|
void *arg;
|
|
|
|
|
{
|
|
|
|
|
int irq;
|
|
|
|
|
struct irqhandler *p;
|
|
|
|
|
u_int iack;
|
|
|
|
|
int res;
|
|
|
|
|
|
|
|
|
|
iack = *((u_int *)(DC21285_PCI_IACK_VBASE));
|
|
|
|
|
iack &= 0xff;
|
|
|
|
|
if (iack < 0x20 || iack > 0x2f) {
|
|
|
|
|
printf("isa_irqdispatch: %x\n", iack);
|
|
|
|
|
return(0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
irq = iack & 0x0f;
|
|
|
|
|
#ifdef IRQSTATS
|
|
|
|
|
++isa_intr_count[irq];
|
|
|
|
|
#endif /* IRQSTATS */
|
|
|
|
|
p = intrhand[irq];
|
|
|
|
|
while (p) {
|
|
|
|
|
#ifdef IRQSTATS
|
|
|
|
|
/* ++p->ih_count;*/
|
|
|
|
|
#endif /* IRQSTATS */
|
|
|
|
|
res = p->ih_func(p->ih_arg);
|
|
|
|
|
p = p->ih_next;
|
|
|
|
|
}
|
|
|
|
|
return(0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
isa_fillw(val, addr, len)
|
|
|
|
|
u_int val;
|
|
|
|
|
void *addr;
|
|
|
|
|
size_t len;
|
|
|
|
|
{
|
|
|
|
|
if ((u_int)addr >= isa_mem_data_vaddr()
|
|
|
|
|
&& (u_int)addr < isa_mem_data_vaddr() + 0x100000) {
|
|
|
|
|
bus_size_t offset = ((u_int)addr) & 0xfffff;
|
|
|
|
|
bus_space_set_region_2(&isa_mem_bs_tag,
|
|
|
|
|
(bus_space_handle_t)isa_mem_bs_tag.bs_cookie, offset,
|
|
|
|
|
val, len);
|
|
|
|
|
} else {
|
|
|
|
|
u_short *ptr = addr;
|
|
|
|
|
|
|
|
|
|
while (len > 0) {
|
|
|
|
|
*ptr++ = val;
|
|
|
|
|
--len;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
chris