e984bd475c
Initialize pba_intrswiz and pba_intrtag before configuring PCI bus.
2002-01-04 22:39:47 +00:00
631447bb4a
Change some #if 0 to #ifdef VERBOSE_INIT_ARM.
2001-12-18 02:52:00 +00:00
5936a89bf5
Add register definitions for the i80200 Interrupt Controller Unit,
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Bus Controller Unit, and Performance Monitoring Unit.
2001-12-01 05:46:19 +00:00
2b08dcc43b
Clarify a comment to state that it is intentional that we attach
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only the Secondary PCI bus (it's the only bus which can have a
device space hidden from any PCI host on the Primary bus).
Also, use the bus number from the PPB businfo register seecondary bus
field rather than hard-coding "1".
2001-11-30 19:29:44 +00:00
e90eccc52c
Clarify a comment.
2001-11-30 19:26:03 +00:00
8ae5055ed9
Add routines for accessing the general purpose I/O facility of
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the i80312 Companion I/O chip.
2001-11-29 08:27:11 +00:00
574dba96b1
Update copyright.
2001-11-29 08:26:18 +00:00
c5ecb8d8c5
Use the new arm_dcache_align variable to set the PCI device BHLC
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register.
2001-11-29 02:26:50 +00:00
636e9cd08b
Add a "cacheline_size" argument to pci_configure_bus(). It is used
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to set the cacheline size in the BHLC register. This should be the
size of the largest D-cache line on a system.
2001-11-28 23:48:34 +00:00
85a1db0fda
Disable MRL, MRM, and MWI for now.
2001-11-28 22:39:09 +00:00
bd3e75a9df
Oops, make sure to add in the physical base of the PCI memory
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window when mapping PCI mem space. (Whee, I can take out my
local hack, now).
2001-11-28 21:08:47 +00:00
fe9e809208
Add a comment explaining that we expect the memory controller
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registers to already be subregion'd off, and actually init
the PCI DMA tag.
2001-11-10 23:14:51 +00:00
d1f4bf74ca
Add support for PCI DMA on the i80312. We currently just do
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DMA via the Secondary Inbound window, for now. Will probably
need to revisit this at some point.
Require that the board-specific i80312 front-end slice off a
subregion for the memory controller before calling i80312_attach(),
and fix a bug in the IQ80310 front-end that caused the Secondary
Inbound window to be configured incorrectly.
2001-11-09 23:15:52 +00:00
d32191e3da
Add support for configuring the PCI bus (starting with the Secondary
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bus only, for now).
XXX Some cleanup wrt. pci_conf_interrupt() needs to happen.
2001-11-09 19:48:35 +00:00
82c11eec1c
Clear the Master Abort after reading config space for a non-existent
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PCI device. Disable debugging messages, as PCI config space works now.
2001-11-09 18:04:10 +00:00
d16c00cfb2
Disable the ATU interrupt sources (i.e. interrupts that occur when
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we get Master or Target aborts).
2001-11-09 17:44:43 +00:00
660b98b7dc
Snapshot of work-in-progress for Intel i80312 Companion I/O chip;
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just basic Inbound and Outbound window setup is done, PCI configuration
space access (not quite working yet), and I/O and Memory space routines
so far.
2001-11-09 03:27:51 +00:00
64f23a2423
Adjust the way the PMMRs are defined -- offsets from a base, not
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absolutes. Also, add PPB and more ATU registers.
2001-11-08 03:20:36 +00:00
af0d2bf570
Config info for the i80312 XScale companion I/O chip.
2001-11-05 23:38:55 +00:00
20b742fd48
RCS ID.
2001-11-05 23:38:05 +00:00
49951f6d12
Prototypes for i80312 routines.
2001-11-05 23:37:41 +00:00
22514e4c7d
Routines for handling the i80312 memory controller for XScale.
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Currently includes a routine to determine memory size from the
SDRAM configuration registers.
2001-11-05 23:37:01 +00:00
fe988b60bb
Add PCI window addresses.
2001-11-04 19:32:32 +00:00
95a9886f49
Add a comment describing what this file is.
2001-11-04 01:23:49 +00:00
8f626436b6
Add missing RCS ID, add missing name.
2001-11-04 01:16:01 +00:00
779b9b4649
Fix some register definitions.
2001-09-05 17:05:36 +00:00
4e642cc5fd
Add i80312 register definitions (just registers for now).
2001-08-26 19:25:47 +00:00
briggs