maps standard boot flags to corresponding RB_* values
use BOOT_FLAG() in port's MD code as appropriate
as discussed on tech-kern, add new boot flags -v, -q for booting
verbosely or quietly, and corresponding AB_VERBOSE/AB_QUIET
boot flags; also add FreeBSD-compatible bootverbose macro and
NetBSD-specific bootquiet macro
for hpcmips, use new bootverbose instead of it's own hpcmips_verbose
Tested on i386, and to limited extend (compile of affected files) also for
mvme68k, hp300, luna68k, sun3.
* All of pmap_init is now deferred to the first call of pmap_create. This
allows us to allocate stuff dynamically using malloc.
* pv_table (which is needed before malloc is available) is temporarily
allocated using pmap_steal_memory in pmap_bootstrap, and then
re-allocated using malloc in pmap_create, with the old allocation being
given back to UVM. This should save some memory on small machines, but
the malloc overhead probably soaks it up.
the fmovecr constant table has the internal format
of the constants. So, when changing the mantissa size by a
non-multiple of 32 bits, we'd have to change this table, too. As
all other code changes just chopped of the least significand
32bit word of the mantissa, we correct the mantissa size instead
to (115 - 32 == 83) bits.
fpu_fmovecr.c:
put a safety belt in, to catch the next person who doesn't know this.
fpu_int.c:
in one place, the reduction of the mantissa size was overlooked.
fpu_log.c:
as the most significand 32bit word of the mantissa was changed back to the
old format, change back the table indexing code, too.
This should fix PR 11045.
indeed tagged with ASM and the ASN, "per the Alpha architecture".
It is therefore safe to cancel any pending lazy I-sync on a
given CPU when a new ASN is assigned on that CPU.
that the page being zero'd was not completed and that page zeroing
should be aborted. This may be used by machine-dependent code doing
slow page access to reduce the latency of running a process that has
become runnable while in the middle of doing a slow page zero.
backend.
The VME2chip can use this to translate a VMEbus irq to a cpu irq.
The VMEchip (on mvme147) can't deal with the VMEbus irq and cpu irq
being different so we just panic in that case for now.
respond in the allotted time if they're told to TALK immediately after
completing a LISTEN command. Experimentation with adb_op_sync() yielded
consistent results when the timeout was increased from the documented
6900 usec to 8000 usec, so we'll make that change here.
(Accurate and complete documentation of the hardware sure would help...)
and a front-end driver for the Ether3. Only semantic change is to remove
ea_claimirq() and ea_releaseirq() on the grounds that the seem too spurious
to warrant a callback to the front-end.
in the MIPS prom loader we have to be very careful how the sections are
ordered and the number of sections defined. For this reason the standard
linker scripts cannot be used.
The exact rules don't appear to be documented and a little experimentation
is required.
and alpha ports.
Uses PROM standalone I/O functions but due to the lack of a lseek function
it currently only works with version 5.40 of the firmware. A more portable
solution is being worked on.
installboot utility requires several changes in order to correctly install
the bootstrap code - there is a "volume directory" which contains a list
of filenames, start sectors and length. We need to add a "boot" entry of
the correct length starting at block 2. The boot file has to be ecoff
which means we waste another 0.5k
Normally the Mips filesystem has a ~500k partition for this purpose but it
should be possible to squeeze it all into the first 7k "BSD Style" (1k is
required for 2 different copies of the partition table)
Only the bootxx_ffs first stage bootstrap has been tested via bootp() which
loads the second stage off disk and then boots the kernel.
in syscall() anymore. By defition, processor was in SR_INT_IE turn
on prior to have syscall exception. MIPS1 assembler hook arranges
to enable the bit for its own. MIPS3 does the same effect by
turning off EXL bit.
fact the direct mapped cache makes address alias effect.
- Just turn on processor master interrupt mask IEc (SR_INT_IE) bit prior
to call syscall() kernel entry point. IEp is always 1 in this case
by defition.
and data cache sizes). R4000 uses 2^(12+IC) and 2^(12+DC). IDT32364
uses 2^(9+IC) and 2^(9+DC).
abstract around the problem by making the base a parameter to the
MIPS3_CONFIG_CACHE_SIZE macro. we pass the base down from mips_vector_init
to mips3_vector_init and to mips3_ConfigCache (where it is used).
XXX: someone with an MIPS3_4100 should switch to this and get rid
of the ugly ifdefs in cpuregs.h
- Don't fall into infinite loop even if the # of iteration necessary isn't 1.
- Don't interpret lower 8bit of AL, which is # of iteration, as a descriptor.
w/ Chuq Silvers. Fixes a panic when a program with wired pages that
has run for a long time when the system is under heavy memory load
exits (specific case was ntpd, reported by Simon Burge).
routine. Works similarly fto pmap_prefer(), but allows callers
to specify a minimum power-of-two alignment of the region.
How we ever got along without this for so long is beyond me.
a whole 0.01us in lmbench lat_syscall null on our 250Mhz QED system.
$at is still saved just to be safe, although it looks like it does
not need to be. $v1 is used in syscall(), although I'm not sure why.
process's segtab, retiring 'pcb_segtab' field from 'struct pcb'.
This would be another MULTIPROCESSOR unfriendly and the necessity
might be eliminated when the way to hold PTE is redesigned.
itohy