c616c9e0fe
use callback function to set up secondary cache related things on arc.
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XXX - perhaps it is better to separate cache related initialization
from mips_vector_init().
2000-03-03 12:43:52 +00:00
67e96268ad
Fix a /dev/kmem crash when vaddr + count wrapped and snuck through
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the error check, courtesy of Jeff Smith <jeffs@geocast.com>.
2000-03-03 02:33:21 +00:00
e48c624741
Loading the exception return PC in k0 before restoring the status register
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(which disables the interrupts) is *not* a good idea. k0 (and k1) is used
by the kernel code such as the TLB miss handler, and the interrupt entry.
If an interrupt occurs after loading k0 and before the SR gets interrupts
disabled, k0 will be clobbered and when used to load the PC on exit from
the exception handler, results in various hangs and crashes.
2000-02-23 17:04:06 +00:00
6ff57360cc
mips is now vm_offset_t/vm_size_t clean
2000-02-22 12:28:25 +00:00
8f03b9a04a
Define the DONETISR macro and use netisr_dispatch.h. This is to cut down on code duplication and to standardize the available NETISRs across all ports.
2000-02-21 20:38:46 +00:00
7f0554e0c9
Add some CONSTCONDs to make lint happier.
2000-02-19 09:23:44 +00:00
09cc3151e6
Don't pull in cpu.h in non-kernel code.
2000-02-19 09:22:51 +00:00
6fe5b35136
Don't print an extra cpu0: prefix.
2000-02-19 04:00:59 +00:00
b4f04eeaad
Disable the sN,sp,gp register restore code for now, as it seems to collide with
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something else.
2000-02-19 01:56:21 +00:00
bb7c9c63f3
On exception return, use k1 to restore the saved registers, so that we
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don't stomp on the return address in k0. Also, don't need to account
for any load delays, as the last register restored (gp) isn't used in
the subsequent instruction.
2000-02-18 18:36:41 +00:00
c9f3b6ba01
Adjust previous change for R3000 load delay slot.
2000-02-18 03:46:43 +00:00
71979ea6fb
Make the MIPS1 and MIPS3 code more similar.
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XXX Needs testing on MIPS1.
2000-02-18 00:15:15 +00:00
9e77fba716
Take a whack at allowing sN, sp and gp to be set from DDB, too.
2000-02-18 00:02:43 +00:00
3ade108e4b
Allow vN, aN, tN, ra, sr, mul[lo,hi] and pc to be set from DDB. sN requires
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more work.
2000-02-17 23:52:23 +00:00
fd8c03cf44
Allow arch-specific code to specify in4_cksum() like it can specify
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in_cksum().
2000-02-14 21:42:50 +00:00
dded044fc2
Update for the NKMEMPAGES changes.
2000-02-11 19:25:12 +00:00
7f5a7c00ac
fix include file.
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<netinet6/ip6.h> -> <netinet/ip6.h>
2000-02-09 05:48:26 +00:00
36e6bc645e
Improve namespace test macros a bit.
2000-02-05 14:04:36 +00:00
82464e46d6
Add a C99-style va_copy macro.
2000-02-03 16:16:06 +00:00
474894e5f6
Fix a bug in cpu_switch() introduced with the MIPSX_CPU_IDLE changes; we
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have a 1 instruction delay after a load before the register contents are
valid on the R2000/R3000.
2000-02-01 18:49:03 +00:00
1247bea5c2
No need for mips_locore_jumpvec to be initialized data.
2000-02-01 18:38:50 +00:00
39bbf02101
Delete unused lines.
2000-01-28 15:18:32 +00:00
ae6160e233
CPU specific idle hook and VR idle routine.
2000-01-28 15:08:36 +00:00
a5cef94d04
We don't really have 'mach trapdump'.
2000-01-26 13:36:05 +00:00
b0fbaa33fb
Remove obsoleted macros.
2000-01-26 09:44:10 +00:00
aa195e816f
Fix PR9240: comment above cpu_fork() out of synch with reality on most ports.
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(comment change only, but was wrong for more than just i386).
2000-01-20 22:18:54 +00:00
a0397a2573
Move callout initialization to a single location; no need to duplicate
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that code all over the place.
2000-01-19 20:05:30 +00:00
b4c00759ec
Clear up a comment a little.
2000-01-09 20:08:14 +00:00
24ddcc3162
Use the badaddr() prototype in mips/include/cpu.h by including
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<machine/cpu.h> in mips/include/mips_param.h. Remove duplicate
badaddr() prototypes from some pmax header files.
2000-01-09 13:24:14 +00:00
ddc897f64e
Prototype stacktrace() and logstacktrace().
2000-01-09 10:05:55 +00:00
5a5de631b0
split 'options SOFTFLOAT' to
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NOFP don't touch FPU registers in kernel
SOFTFLOAT emulate FPU instructions in kernel
2000-01-09 08:01:54 +00:00
693059feda
const -> __const and include <sys/cdefs.h> earlier; fixes PR lib/9052
...
by Takahiro Kambe.
2000-01-04 14:20:05 +00:00
7fc2807b2b
Make SOFTFLOAT emulation compatible with _MIPS_BSD_API_LP32_64CLEAN
1999-12-29 04:41:12 +00:00
2a0deb6e74
Add code to ensure delay slot is printed when disassembling.
1999-12-27 21:12:25 +00:00
cf643fe983
Add macro for MIPS_PHYS_MASK and document use of bits in system status
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registers.
1999-12-27 20:05:06 +00:00
11e6c54cfc
C99: Define a NAN macro in <math.h> which evaulates to a constant expression of
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a single-precision quiet NaN; only to be defined on platforms that do support
this value.
1999-12-23 10:15:05 +00:00
ea69e534d2
* news5000 support.
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* mips3_VCE[DI] now support L2CacheLSize != 32.
1999-12-22 05:54:18 +00:00
2db6d32929
FIX:
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port-mips/9016 [serious/medium]:
MIPS FPU emulator points wrong epc on exception case
Responsible: port-mips-maintainer (NetBSD/mips Portmasters)
State: open
Class: sw-bug
Originator: Shuichiro URATA
Release: current 12/11/1999
Arrival-Date: Fri Dec 17 10:18:00 1999
commit patch
http://www.a-r.org/~ur/softfloat1211.diff.gz
by Shuichiro URATA (ur@a-r.org )
1999-12-22 04:54:14 +00:00
f981fe2ed7
Don't need "extern int physmem" - <sys/systm.h> has this already.
1999-12-11 14:05:04 +00:00
855917ea08
Fix typo on _MIPS_BSD_API switch.
1999-12-09 15:39:46 +00:00
b6113c1d8c
delete clrnd() to compile again.
1999-12-05 03:31:11 +00:00
0513268399
CL* discarding.
1999-12-04 21:13:19 +00:00
ba72fb5211
Decouple DECstation binding, use 'dev/dec/mcclock_pad32.h' for
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implementation consistency.
1999-12-03 02:56:37 +00:00
31f8115d20
Add _splrestore() to manipulate processor interrupt control bits.
1999-12-03 02:15:55 +00:00
ccba32ca1d
reorder instructions in mips3_TLBFlush() to avoid coprocessor hazard
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for R4600/R4700/VR4100.
1999-11-30 11:53:24 +00:00
878e985d08
Some TX39 I/O region lies over 512MByte. KSEG2IOBUFSIZE reserves PTE to map there.
1999-11-29 11:14:49 +00:00
8b01b15437
TX3912/22 specific register defines.
1999-11-29 11:13:11 +00:00
347ea4cd91
TX3912/22 support. ENABLE_MIPS_TX3900 enables it.
1999-11-29 11:12:12 +00:00
49ead2a4a7
add RCS Id.
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add copyright & license notice.
1999-11-22 02:11:09 +00:00
46b5560f98
and add sys/arch/mips/mips/fpemu.c
1999-11-18 06:50:17 +00:00
soda