this insn is available only on ARM arch v3 and later (and 2a). We
don't expect to be using these ops in the kernel on processors too
old to have SWP, and for userland uses (in e.g. a pthread library),
the kernel will simply have to trap and emulate the insn (it needs
to be "atomic", so a kernel trap of some sort will be necessary on
such platforms anyway).
the Branch Target Buffer of the BPRD bit changes.
* Enable Branch Prediction on the XScale by default.
* Don't invalidate the Branch Target Buffer explicitly. the i80200
manual (section 5.1, Branch Target Buffer Operation) notes that
manual software management of the BTB is unnecessary; it is flushed
implicitly when:
* processor resets
* FCSE process ID is written
* I-cache is invalidated
pages, we use the standard (4K) page size as PAGE_SIZE. Make the
PAGE_SIZE related variables compile-time constants that reflect this.
Results in a bit over 2K worth of .text savings, and visibly better
code in the places that use PAGE_SIZE, etc.
support it in the kernel yet. If we don't do this, GDB arbitrarily
assumes we wanted it to be 9, which is silly.
In the kernel, leave it undefined so that sys_process.c doesn't
generate code for it.
the instruction we used with GDB 4.x. The new instruction has the advantage
of fitting the pattern that ARM recommend using for instructions that need to
stay undefined.
This will allow improvements to the pmaps so that they can more easily defer expensive operations, eg tlb/cache flush, til the last possible moment.
Currently this is a no-op on most platforms, so they should see no difference.
Reviewed by Jason.
Thorpe as an extension to the bus_space(9) API.
Only the mainbus has a working mmap... iomd, podulebus and isa dont have
one yet. Its trivial to add the iomd and isa's memory part but am a bit
hessistant to add it without knowing its implications by heart.
Podulebus might be implemented in 32 bits EASI but otherwise its not really
transparent since there is AFAIK no function to explicitly read one byte or
so .. or is this implemented in a higher level ?
ARM26 and arch/arm32/dnard (Shark) kernels compile and RiscPC and Shark
kernels are tested and function OK.
Implications of other ARM systems like hpcarm and ebarm are propably
minimal or solved trivially.
Improved locking (not that we actually use it on a uniprocessor, but one day :)
Removed unneeded splvm's
tweaked pmap_clean_page code to only flush the cache if the page is mapped in the current pmap (based on diff from richard E)
Adopted pv entry allocation mechanism from i386.
Laid framework for returning ptp's when we've finished with them rather than holding onto them till the process exits.
ptp's are now allocated with a uvm object for the pmap, means that we can walk a list to free them off in pmap_release, until they get freed off by pmap_remove.
Also implemented a page zeroing function when the processor is idling. Note that hpcarm may wish to disable this.
I believe this code to be stable, if anyone has any problems please shout up.
bootable GENERAL kernel for the 3 machines.
This is done by integrating the ARM7500 in a better way. In various places
the IOMD ID is checked and action is taken at runtime compared to
compiletime.
The small piece of assembler that is changed now uses the flag
`arm7500_ioc_found' that is set up by iomd.c at startup. When this chip
isnt found at startup it will skip reading the ARM7500 extended IRQ
registers and wont clear them either.
The next step will be getting the mode-definition files to the bootloader.
Currently they are compiled in.
Note that I've some ideas in the works on how to improve the pv handling, so the slow down is short term only.
Also added non-advertising licence and copyright to myself and richard.
instruction that stores the program counter and the value of PC that's stored.
This can vary between ARM implementations, but is guaranteed to be constant on
a given one.
and late_abort_fixup(), based on the abort model in use, rather than the CPU
type. This cleans up the code and makes it smaller. Only tested on an
ARM6 -- I can't find my ARM710a card right now.
- use "U" suffix for unsigned constants
- use "L" suffix for long constants
- use "UL" suffix for unsigned long constants
- use hexadecimal instead of decimal
Fixes build problems with vi (now that warnings/errors are enabled) on
mips, powerpc and arm platforms.
to <sys/types.h> and <sys/stdint.h>.
* Add a new C99 <stdint.h> header, which provides integer types of
explicit width, related limits and integer constant macros.
* Extend <inttypes.h> to provide <stdint.h> definitions and format
macros for printf() and scanf().
* Add C99 strtoimax() and strtoumax() functions.
* Use the latter within scanf().
* Add C99 %j, %t and %z printf()/scanf() conversions for
intmax_t, pointer-type and size_t arguments.
co-processor. This is necessary so we can have several handlers for
CP0 (used as a catch-all for non-CP instructions).
Handlers are now removed using remove_coproc_handler(), rather than by calling
install_coproc_handler() with a NULL handler.
Because install_coproc_handler() can now allocate memory, there's a version
for use at boot time that doesn't.
support, which corresponds to one for each CPU_* option, or one for each
cpufunc structure.
Also remove some more residual code for the support of multiple and non-ARM
CPUs.
Move the pointer to the current user trapframe from struct mdproc to struct
pcb (as on arm26). Only tested by compiling kernels on arm32 and
hpcarm (dnard seems to be incomplete anyway). Someone should try running one.
tree into the new arm substree. All moved files are relinked with a stub that included
the file from the new location; this might be done better later.
Note that I'm using __VFP_FP__ to indicate compilation with VFP-format
floating-point data. There doesn't (currently) seem to be a standard define
for this purpose. __VFP_FP__ was suggested by Richard Earnshaw.
shape as the old arm32 one, but there are a few #defines to keep arm26 code
happy. Anything that depends on the precise shape of the trapframe,
and especially on being able to treat it as an array of registers, has been
updated.
bjh21