Initial potentially sharable <arm/armreg.h>. Used by all arm26 code.
This commit is contained in:
bjh21
parent
a07a06dd78
commit
1178bf4219
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@ -1,9 +1,9 @@
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# $NetBSD: Makefile,v 1.5 2001/01/18 21:48:25 bjh21 Exp $
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# $NetBSD: Makefile,v 1.6 2001/01/22 22:10:39 bjh21 Exp $
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KDIR= /sys/arch/arm/include
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INCSDIR= /usr/include/arm
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INCS= ansi.h aout_machdep.h asm.h bswap.h cdefs.h disklabel.h \
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INCS= ansi.h aout_machdep.h armreg.h asm.h bswap.h cdefs.h disklabel.h \
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disklabel_acorn.h elf_machdep.h float.h fp.h frame.h ieee.h ieeefp.h \
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int_types.h limits.h lock.h math.h signal.h setjmp.h stdarg.h \
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trap.h varargs.h
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@ -0,0 +1,267 @@
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/* $NetBSD: armreg.h,v 1.1 2001/01/22 22:10:40 bjh21 Exp $ */
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/*
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* Copyright (c) 1998, 2001 Ben Harris
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* Copyright (c) 1994-1996 Mark Brinicombe.
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* Copyright (c) 1994 Brini.
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Brini.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _ARM_ARMREG_H
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#define _ARM_ARMREG_H
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/*
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* ARM Process Status Register
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*
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* The picture in the ARM manuals looks like this:
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* 3 3 2 2 2 2
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* 1 0 9 8 7 6 8 7 6 5 4 0
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* +-+-+-+-+-+-------------------------------------+-+-+-+---------+
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* |N|Z|C|V|Q| reserved |I|F|T|M M M M M|
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* | | | | | | | | | |4 3 2 1 0|
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* +-+-+-+-+-+-------------------------------------+-+-+-+---------+
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*/
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#define PSR_FLAGS 0xf0000000 /* flags */
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#define PSR_N_bit (1 << 31) /* negative */
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#define PSR_Z_bit (1 << 30) /* zero */
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#define PSR_C_bit (1 << 29) /* carry */
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#define PSR_V_bit (1 << 28) /* overflow */
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#define PSR_Q_bit (1 << 27) /* saturation */
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#define I32_bit (1 << 7) /* IRQ disable */
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#define F32_bit (1 << 6) /* FIQ disable */
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#define PSR_T_bit (1 << 5) /* Thumb state */
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#define PSR_MODE 0x0000001f /* mode mask */
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#define PSR_USR26_MODE 0x00000000
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#define PSR_FIQ26_MODE 0x00000001
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#define PSR_IRQ26_MODE 0x00000002
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#define PSR_SVC26_MODE 0x00000003
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#define PSR_USR32_MODE 0x00000010
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#define PSR_FIQ32_MODE 0x00000011
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#define PSR_IRQ32_MODE 0x00000012
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#define PSR_SVC32_MODE 0x00000013
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#define PSR_ABT32_MODE 0x00000017
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#define PSR_UND32_MODE 0x0000001b
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#define PSR_SYS32_MODE 0x0000001f
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#define PSR_32_MODE 0x00000010
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#define PSR_IN_USR_MODE(psr) (!((psr) & 3)) /* XXX */
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#define PSR_IN_32_MODE(psr) ((psr) & PSR_32_MODE)
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/* In 26-bit modes, the PSR is stuffed into R15 along with the PC. */
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#define R15_MODE 0x00000003
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#define R15_MODE_USR 0x00000000
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#define R15_MODE_FIQ 0x00000001
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#define R15_MODE_IRQ 0x00000002
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#define R15_MODE_SVC 0x00000003
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#define R15_PC 0x03fffffc
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#define R15_FIQ_DISABLE 0x04000000
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#define R15_IRQ_DISABLE 0x08000000
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#define R15_FLAGS 0xf0000000
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#define R15_FLAG_N 0x80000000
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#define R15_FLAG_Z 0x40000000
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#define R15_FLAG_C 0x20000000
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#define R15_FLAG_V 0x10000000
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/*
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* Co-processor 15: The system control co-processor.
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*/
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#define ARM_CP15_CPU_ID 0
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/*
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* The CPU ID register is theoretically structured, but the definitions of
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* the fields keep changing.
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*/
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/* The high-order byte is always the implementor */
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#define CPU_ID_IMPLEMENTOR_MASK 0xff000000
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#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */
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#define CPU_ID_DEC 0x44000000 /* 'D' */
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#define CPU_ID_INTEL 0x69000000 /* 'i' */
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/* On ARM3 and ARM6, this byte holds the foundry ID. */
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#define CPU_ID_FOUNDRY_MASK 0x00ff0000
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#define CPU_ID_FOUNDRY_VLSI 0x00560000
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/* On ARM7 it holds the architecture and variant (sub-model) */
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#define CPU_ID_7ARCH_MASK 0x00800000
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#define CPU_ID_7ARCH_V3 0x00000000
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#define CPU_ID_7ARCH_V4T 0x00800000
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#define CPU_ID_7VARIANT_MASK 0x007f0000
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/* On more recent ARMs, it does the same, but in a different format */
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#define CPU_ID_ARCH_MASK 0x000f0000
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#define CPU_ID_ARCH_V3 0x00000000
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#define CPU_ID_ARCH_V4 0x00010000
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#define CPU_ID_ARCH_V4T 0x00020000
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#define CPU_ID_ARCH_V5 0x00030000
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#define CPU_ID_ARCH_V5T 0x00040000
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#define CPU_ID_ARCH_V5TE 0x00050000
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#define CPU_ID_VARIANT_MASK 0x00f00000
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/* Next three nybbles are part number */
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#define CPU_ID_PARTNO_MASK 0x0000fff0
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#define CPU_ID_CPU_MASK CPU_ID_PARTNO_MASK
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/* And finally, the revision number. */
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#define CPU_ID_REVISION_MASK 0x0000000f
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/* Fake CPU IDs for ARMs without CP15 */
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#define CPU_ID_ARM2 0x41560200
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#define CPU_ID_ARM250 0x41560250
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/* Pre-ARM7 CPUs -- [15:12] == 0 */
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#define CPU_ID_ARM3 0x41560300
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#define CPU_ID_ARM600 0x41560600
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#define CPU_ID_ARM610 0x41560610
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#define CPU_ID_ARM620 0x41560620
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/* ARM7 CPUs -- [15:12] == 7 */
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#define CPU_ID_ARM710 0x41007100
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#define CPU_ID_ARM7100 0x41047100
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#define CPU_ID_ARM710T 0x41807100
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#define CPU_ID_ARM720T 0x41807200
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#define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */
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#define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */
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/* Post-ARM7 CPUs */
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#define CPU_ID_ARM810 0x41018100
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#define CPU_ID_ARM920T 0x41129200
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#define CPU_ID_ARM922T 0x41029220
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#define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */
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#define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */
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#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */
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#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */
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#define CPU_ID_SA110 0x4401a100
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#define CPU_ID_SA1100 0x4401a110
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#define CPU_ID_SA1110 0x6901b110
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#define CPU_ID_I80200 0x69052000 /* XScale core */
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#define CPU_ID_ARM700 0x00007000
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/* ARM3-specific coprocessor 15 registers */
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#define ARM3_CP15_FLUSH 1
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#define ARM3_CP15_CONTROL 2
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#define ARM3_CP15_CACHEABLE 3
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#define ARM3_CP15_UPDATEABLE 4
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#define ARM3_CP15_DISRUPTIVE 5
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/* ARM3 Control register bits */
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#define ARM3_CTL_CACHE_ON 0x00000001
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#define ARM3_CTL_SHARED 0x00000002
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#define ARM3_CTL_MONITOR 0x00000004
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/*
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* Post-ARM3 CP15 registers:
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*/
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/* Some of the definitions below need cleaning up for V3/V4 architectures */
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/* CPU control register (CP15 register 1) */
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#define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */
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#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */
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#define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */
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#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */
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#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */
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#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */
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#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */
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#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */
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#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */
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#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */
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#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */
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#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */
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#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */
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#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */
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#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */
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#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */
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#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE
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/* Cache type register definitions */
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#define CPU_CT_IINFO_MASK 0x00000fff
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#define CPU_CT_IINFO_SHIFT 0
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#define CPU_CT_DINFO_MASK 0x00fff000
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#define CPU_CT_DINFO_SHIFT 12
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#define CPU_CT_HARVARD 0x01000000
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#define CPU_CT_TYPE_MASK 0x1e000000
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/* "Info" subfields -- see ARM ARM for meanings. */
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#define CPU_CT_LINE_MASK 0x00000003
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#define CPU_CT_M_BIT 0x00000004
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#define CPU_CT_ASSOC_MASK 0x00000038
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#define CPU_CT_SIZE_MASK 0x000001c0
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/* Fault status register definitions */
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#define FAULT_TYPE_MASK 0x0f
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#define FAULT_USER 0x10
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#define FAULT_WRTBUF_0 0x00 /* Vector Exception */
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#define FAULT_WRTBUF_1 0x02 /* Terminal Exception */
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#define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */
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#define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */
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#define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */
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#define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */
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#define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */
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#define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */
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#define FAULT_ALIGN_0 0x01 /* Alignment */
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#define FAULT_ALIGN_1 0x03 /* Alignment */
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#define FAULT_TRANS_S 0x05 /* Translation -- Section */
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#define FAULT_TRANS_P 0x07 /* Translation -- Page */
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#define FAULT_DOMAIN_S 0x09 /* Domain -- Section */
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#define FAULT_DOMAIN_P 0x0b /* Domain -- Page */
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#define FAULT_PERM_S 0x0d /* Permission -- Section */
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#define FAULT_PERM_P 0x0f /* Permission -- Page */
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/*
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* ARM Instructions
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*
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* 3 3 2 2 2
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* 1 0 9 8 7 0
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* +-------+-------------------------------------------------------+
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* | cond | instruction dependant |
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* |c c c c| |
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* +-------+-------------------------------------------------------+
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*/
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#define INSN_SIZE 4 /* Always 4 bytes */
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#define INSN_COND_MASK 0xf0000000 /* Condition mask */
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#define INSN_COND_AL 0xe0000000 /* Always condition */
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#endif
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu.c,v 1.3 2000/12/23 13:37:03 bjh21 Exp $ */
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/* $NetBSD: cpu.c,v 1.4 2001/01/22 22:10:41 bjh21 Exp $ */
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/*-
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* Copyright (c) 2000 Ben Harris
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@ -33,14 +33,14 @@
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#include <sys/param.h>
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__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.3 2000/12/23 13:37:03 bjh21 Exp $");
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__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.4 2001/01/22 22:10:41 bjh21 Exp $");
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#include <sys/device.h>
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#include <sys/proc.h>
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#include <sys/systm.h>
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#include <sys/time.h>
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#include <sys/user.h>
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#include <machine/armreg.h>
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#include <arm/armreg.h>
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#include <machine/machdep.h>
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#include <machine/pcb.h>
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/* $NetBSD: db_trace.c,v 1.5 2001/01/18 17:05:06 bjh21 Exp $ */
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/* $NetBSD: db_trace.c,v 1.6 2001/01/22 22:10:42 bjh21 Exp $ */
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/*
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* Copyright (c) 1996 Scott K. Stevens
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@ -29,9 +29,12 @@
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*/
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#include <sys/param.h>
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__RCSID("$NetBSD: db_trace.c,v 1.6 2001/01/22 22:10:42 bjh21 Exp $");
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#include <sys/proc.h>
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#include <sys/user.h>
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#include <machine/armreg.h>
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#include <arm/armreg.h>
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#include <machine/db_machdep.h>
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#include <ddb/db_access.h>
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/* $NetBSD: except.c,v 1.25 2001/01/20 17:14:20 bjh21 Exp $ */
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/* $NetBSD: except.c,v 1.26 2001/01/22 22:10:42 bjh21 Exp $ */
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/*-
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* Copyright (c) 1998, 1999, 2000 Ben Harris
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* All rights reserved.
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@ -32,7 +32,7 @@
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#include <sys/param.h>
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__KERNEL_RCSID(0, "$NetBSD: except.c,v 1.25 2001/01/20 17:14:20 bjh21 Exp $");
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__KERNEL_RCSID(0, "$NetBSD: except.c,v 1.26 2001/01/22 22:10:42 bjh21 Exp $");
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#include "opt_cputypes.h"
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#include "opt_ddb.h"
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#include <uvm/uvm_extern.h>
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#include <machine/armreg.h>
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#include <arm/armreg.h>
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#include <machine/intr.h>
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#include <machine/machdep.h>
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#include <machine/pcb.h>
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.S,v 1.10 2001/01/20 17:14:20 bjh21 Exp $ */
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/* $NetBSD: locore.S,v 1.11 2001/01/22 22:10:43 bjh21 Exp $ */
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/*
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* Copyright (c) 1998, 1999, 2000 Ben Harris
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* Copyright (C) 1994-1997 Mark Brinicombe
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@ -41,7 +41,7 @@
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/* RCSID is at the end of the file in case it gets put in the text segment. */
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#include <sys/syscall.h>
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#include <machine/armreg.h>
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#include <arm/armreg.h>
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#include "assym.h"
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#include "opt_cputypes.h"
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@ -456,4 +456,4 @@ _C_LABEL(intrcnt):
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.global _C_LABEL(eintrcnt)
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_C_LABEL(eintrcnt):
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RCSID("$NetBSD: locore.S,v 1.10 2001/01/20 17:14:20 bjh21 Exp $")
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RCSID("$NetBSD: locore.S,v 1.11 2001/01/22 22:10:43 bjh21 Exp $")
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@ -1,4 +1,4 @@
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/* $NetBSD: process_machdep.c,v 1.1 2000/08/20 15:16:51 bjh21 Exp $ */
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/* $NetBSD: process_machdep.c,v 1.2 2001/01/22 22:10:43 bjh21 Exp $ */
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/*-
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* Copyright (c) 2000 Ben Harris
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* All rights reserved.
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@ -32,14 +32,14 @@
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#include <sys/param.h>
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__RCSID("$NetBSD: process_machdep.c,v 1.1 2000/08/20 15:16:51 bjh21 Exp $");
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__RCSID("$NetBSD: process_machdep.c,v 1.2 2001/01/22 22:10:43 bjh21 Exp $");
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#include <sys/errno.h>
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#include <sys/proc.h>
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#include <sys/ptrace.h>
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#include <sys/user.h>
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#include <machine/armreg.h>
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#include <arm/armreg.h>
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#include <machine/frame.h>
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||||
#include <machine/pcb.h>
|
||||
#include <machine/reg.h>
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: start.c,v 1.7 2000/12/27 20:43:44 bjh21 Exp $ */
|
||||
/* $NetBSD: start.c,v 1.8 2001/01/22 22:10:43 bjh21 Exp $ */
|
||||
/*-
|
||||
* Copyright (c) 1998, 2000 Ben Harris
|
||||
* All rights reserved.
|
||||
|
|
@ -32,14 +32,14 @@
|
|||
|
||||
#include <sys/param.h>
|
||||
|
||||
__KERNEL_RCSID(0, "$NetBSD: start.c,v 1.7 2000/12/27 20:43:44 bjh21 Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: start.c,v 1.8 2001/01/22 22:10:43 bjh21 Exp $");
|
||||
|
||||
#include <sys/msgbuf.h>
|
||||
#include <sys/user.h>
|
||||
#include <sys/syslog.h>
|
||||
#include <sys/systm.h>
|
||||
|
||||
#include <machine/armreg.h>
|
||||
#include <arm/armreg.h>
|
||||
#include <machine/boot.h>
|
||||
#include <machine/machdep.h>
|
||||
#include <machine/memcreg.h>
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: vm_machdep.c,v 1.10 2001/01/16 00:29:45 bjh21 Exp $ */
|
||||
/* $NetBSD: vm_machdep.c,v 1.11 2001/01/22 22:10:44 bjh21 Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2000, 2001 Ben Harris
|
||||
|
|
@ -66,7 +66,7 @@
|
|||
|
||||
#include <sys/param.h>
|
||||
|
||||
__RCSID("$NetBSD: vm_machdep.c,v 1.10 2001/01/16 00:29:45 bjh21 Exp $");
|
||||
__RCSID("$NetBSD: vm_machdep.c,v 1.11 2001/01/22 22:10:44 bjh21 Exp $");
|
||||
|
||||
#include <sys/buf.h>
|
||||
#include <sys/exec.h>
|
||||
|
|
@ -77,7 +77,7 @@ __RCSID("$NetBSD: vm_machdep.c,v 1.10 2001/01/16 00:29:45 bjh21 Exp $");
|
|||
|
||||
#include <uvm/uvm_extern.h>
|
||||
|
||||
#include <machine/armreg.h>
|
||||
#include <arm/armreg.h>
|
||||
#include <machine/frame.h>
|
||||
#include <machine/intr.h>
|
||||
#include <machine/machdep.h>
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
# $NetBSD: Makefile,v 1.3 2000/08/22 21:27:21 bjh21 Exp $
|
||||
# $NetBSD: Makefile,v 1.4 2001/01/22 22:10:44 bjh21 Exp $
|
||||
|
||||
KDIR= /sys/arch/arm26/include
|
||||
INCSDIR= /usr/include/arm26
|
||||
|
||||
INCS= ansi.h aout_machdep.h armreg.h asm.h boot.h bswap.h bus.h cdefs.h \
|
||||
INCS= ansi.h aout_machdep.h asm.h boot.h bswap.h bus.h cdefs.h \
|
||||
cpu.h db_machdep.h disklabel.h \
|
||||
disklabel_acorn.h elf_machdep.h endian.h endian_machdep.h float.h \
|
||||
fp.h frame.h ieee.h ieeefp.h int_types.h intr.h ipkdb.h irq.h \
|
||||
|
|
|
|||
|
|
@ -1,79 +0,0 @@
|
|||
/* $NetBSD: armreg.h,v 1.1 2000/05/09 21:55:58 bjh21 Exp $ */
|
||||
/*-
|
||||
* Copyright (c) 1998 Ben Harris
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
/* This file is part of NetBSD/arm26 -- a port of NetBSD to ARM2/3 machines. */
|
||||
|
||||
#ifndef _ARM26_ARMREG_H
|
||||
#define _ARM26_ARMREG_H
|
||||
|
||||
/* All the junk the old ARMs stuff in R15 */
|
||||
|
||||
#define R15_MODE 0x00000003
|
||||
#define R15_MODE_USR 0x00000000
|
||||
#define R15_MODE_FIQ 0x00000001
|
||||
#define R15_MODE_IRQ 0x00000002
|
||||
#define R15_MODE_SVC 0x00000003
|
||||
|
||||
#define R15_PC 0x03fffffc
|
||||
|
||||
#define R15_FIQ_DISABLE 0x04000000
|
||||
#define R15_IRQ_DISABLE 0x08000000
|
||||
|
||||
#define R15_FLAGS 0xf0000000
|
||||
#define R15_FLAG_N 0x80000000
|
||||
#define R15_FLAG_Z 0x40000000
|
||||
#define R15_FLAG_C 0x20000000
|
||||
#define R15_FLAG_V 0x10000000
|
||||
|
||||
#define ARM_CP15_CPU_ID 0
|
||||
|
||||
/* Not really many CPUs to consider */
|
||||
#define CPU_ID_DESIGNER_MASK 0xff000000
|
||||
#define CPU_ID_ARM_LTD 0x41000000
|
||||
#define CPU_ID_TYPE_MASK 0x00ff0000
|
||||
#define CPU_ID_ARM 0x00560000
|
||||
#define CPU_ID_CPU_MASK 0x0000fff0
|
||||
#define CPU_ID_ARM3 0x00000300
|
||||
#define CPU_ID_REVISION_MASK 0x0000000f
|
||||
|
||||
/* Fake CPU IDs for older ARMs */
|
||||
#define CPU_ID_ARM2 0x00000200
|
||||
#define CPU_ID_ARM250 0x00000250
|
||||
|
||||
/* ARM3-specific coprocessor 15 register */
|
||||
#define ARM3_CP15_FLUSH 1
|
||||
#define ARM3_CP15_CONTROL 2
|
||||
#define ARM3_CP15_CACHEABLE 3
|
||||
#define ARM3_CP15_UPDATEABLE 4
|
||||
#define ARM3_CP15_DISRUPTIVE 5
|
||||
|
||||
/* Control register bits */
|
||||
#define ARM3_CTL_CACHE_ON 1
|
||||
#define ARM3_CTL_SHARED 2
|
||||
#define ARM3_CTL_MONITOR 4
|
||||
|
||||
#endif
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: db_machdep.h,v 1.3 2000/12/10 01:31:48 bjh21 Exp $ */
|
||||
/* $NetBSD: db_machdep.h,v 1.4 2001/01/22 22:10:45 bjh21 Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1996 Scott K Stevens
|
||||
|
|
@ -36,7 +36,7 @@
|
|||
*/
|
||||
|
||||
#include <uvm/uvm_extern.h>
|
||||
#include <machine/armreg.h>
|
||||
#include <arm/armreg.h>
|
||||
#include <machine/frame.h>
|
||||
|
||||
typedef vm_offset_t db_addr_t; /* address - unsigned */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: frame.h,v 1.4 2001/01/20 17:14:20 bjh21 Exp $ */
|
||||
/* $NetBSD: frame.h,v 1.5 2001/01/22 22:10:46 bjh21 Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1999 Ben Harris.
|
||||
|
|
@ -46,7 +46,7 @@
|
|||
|
||||
#ifndef _LOCORE
|
||||
|
||||
#include <machine/armreg.h>
|
||||
#include <arm/armreg.h>
|
||||
|
||||
/*
|
||||
* System stack frames.
|
||||
|
|
|
|||
Loading…
Reference in New Issue