diff --git a/sys/arch/arm/include/Makefile b/sys/arch/arm/include/Makefile
index 12eaccb98812..df0795bb35d0 100644
--- a/sys/arch/arm/include/Makefile
+++ b/sys/arch/arm/include/Makefile
@@ -1,9 +1,9 @@
-#	$NetBSD: Makefile,v 1.5 2001/01/18 21:48:25 bjh21 Exp $
+#	$NetBSD: Makefile,v 1.6 2001/01/22 22:10:39 bjh21 Exp $
 
 KDIR=	/sys/arch/arm/include
 INCSDIR= /usr/include/arm
 
-INCS=	ansi.h aout_machdep.h asm.h bswap.h cdefs.h disklabel.h \
+INCS=	ansi.h aout_machdep.h armreg.h asm.h bswap.h cdefs.h disklabel.h \
 	disklabel_acorn.h elf_machdep.h float.h fp.h frame.h ieee.h ieeefp.h \
 	int_types.h limits.h lock.h math.h signal.h setjmp.h stdarg.h \
 	trap.h varargs.h
diff --git a/sys/arch/arm/include/armreg.h b/sys/arch/arm/include/armreg.h
new file mode 100644
index 000000000000..eba9a67ce5ab
--- /dev/null
+++ b/sys/arch/arm/include/armreg.h
@@ -0,0 +1,267 @@
+/*	$NetBSD: armreg.h,v 1.1 2001/01/22 22:10:40 bjh21 Exp $	*/
+
+/*
+ * Copyright (c) 1998, 2001 Ben Harris
+ * Copyright (c) 1994-1996 Mark Brinicombe.
+ * Copyright (c) 1994 Brini.
+ * All rights reserved.
+ *
+ * This code is derived from software written for Brini by Mark Brinicombe
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Brini.
+ * 4. The name of the company nor the name of the author may be used to
+ *    endorse or promote products derived from this software without specific
+ *    prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _ARM_ARMREG_H
+#define _ARM_ARMREG_H
+
+/*
+ * ARM Process Status Register
+ *
+ * The picture in the ARM manuals looks like this:
+ *       3 3 2 2 2 2                            
+ *       1 0 9 8 7 6                                   8 7 6 5 4       0
+ *      +-+-+-+-+-+-------------------------------------+-+-+-+---------+
+ *      |N|Z|C|V|Q|                reserved             |I|F|T|M M M M M|
+ *      | | | | | |                                     | | | |4 3 2 1 0|
+ *      +-+-+-+-+-+-------------------------------------+-+-+-+---------+
+ */
+
+#define	PSR_FLAGS 0xf0000000	/* flags */
+#define PSR_N_bit (1 << 31)	/* negative */
+#define PSR_Z_bit (1 << 30)	/* zero */
+#define PSR_C_bit (1 << 29)	/* carry */
+#define PSR_V_bit (1 << 28)	/* overflow */
+
+#define PSR_Q_bit (1 << 27)	/* saturation */
+
+#define I32_bit (1 << 7)	/* IRQ disable */
+#define F32_bit (1 << 6)	/* FIQ disable */
+
+#define PSR_T_bit (1 << 5)	/* Thumb state */
+
+#define PSR_MODE	0x0000001f	/* mode mask */
+#define PSR_USR26_MODE	0x00000000
+#define PSR_FIQ26_MODE	0x00000001
+#define PSR_IRQ26_MODE	0x00000002
+#define PSR_SVC26_MODE	0x00000003
+#define PSR_USR32_MODE	0x00000010
+#define PSR_FIQ32_MODE	0x00000011
+#define PSR_IRQ32_MODE	0x00000012
+#define PSR_SVC32_MODE	0x00000013
+#define PSR_ABT32_MODE	0x00000017
+#define PSR_UND32_MODE	0x0000001b
+#define PSR_SYS32_MODE	0x0000001f
+#define PSR_32_MODE	0x00000010
+
+#define PSR_IN_USR_MODE(psr)	(!((psr) & 3))		/* XXX */
+#define PSR_IN_32_MODE(psr)	((psr) & PSR_32_MODE)
+
+/* In 26-bit modes, the PSR is stuffed into R15 along with the PC. */
+
+#define R15_MODE	0x00000003
+#define R15_MODE_USR	0x00000000
+#define R15_MODE_FIQ	0x00000001
+#define R15_MODE_IRQ	0x00000002
+#define R15_MODE_SVC	0x00000003
+
+#define R15_PC		0x03fffffc
+
+#define R15_FIQ_DISABLE	0x04000000
+#define R15_IRQ_DISABLE	0x08000000
+
+#define R15_FLAGS	0xf0000000
+#define R15_FLAG_N	0x80000000
+#define R15_FLAG_Z	0x40000000
+#define R15_FLAG_C	0x20000000
+#define R15_FLAG_V	0x10000000
+
+/*
+ * Co-processor 15:  The system control co-processor.
+ */
+
+#define ARM_CP15_CPU_ID		0
+
+/*
+ * The CPU ID register is theoretically structured, but the definitions of
+ * the fields keep changing.
+ */
+
+/* The high-order byte is always the implementor */
+#define CPU_ID_IMPLEMENTOR_MASK	0xff000000
+#define CPU_ID_ARM_LTD		0x41000000 /* 'A' */
+#define CPU_ID_DEC		0x44000000 /* 'D' */
+#define CPU_ID_INTEL		0x69000000 /* 'i' */
+
+/* On ARM3 and ARM6, this byte holds the foundry ID. */
+#define CPU_ID_FOUNDRY_MASK	0x00ff0000
+#define CPU_ID_FOUNDRY_VLSI	0x00560000
+
+/* On ARM7 it holds the architecture and variant (sub-model) */
+#define CPU_ID_7ARCH_MASK	0x00800000
+#define CPU_ID_7ARCH_V3		0x00000000
+#define CPU_ID_7ARCH_V4T	0x00800000
+#define CPU_ID_7VARIANT_MASK	0x007f0000
+
+/* On more recent ARMs, it does the same, but in a different format */
+#define CPU_ID_ARCH_MASK	0x000f0000
+#define CPU_ID_ARCH_V3		0x00000000
+#define CPU_ID_ARCH_V4		0x00010000
+#define CPU_ID_ARCH_V4T		0x00020000
+#define CPU_ID_ARCH_V5		0x00030000
+#define CPU_ID_ARCH_V5T		0x00040000
+#define CPU_ID_ARCH_V5TE	0x00050000
+#define CPU_ID_VARIANT_MASK	0x00f00000
+
+/* Next three nybbles are part number */
+#define CPU_ID_PARTNO_MASK	0x0000fff0
+#define CPU_ID_CPU_MASK		CPU_ID_PARTNO_MASK
+
+/* And finally, the revision number. */
+#define CPU_ID_REVISION_MASK	0x0000000f
+
+/* Fake CPU IDs for ARMs without CP15 */
+#define CPU_ID_ARM2		0x41560200
+#define CPU_ID_ARM250		0x41560250
+
+/* Pre-ARM7 CPUs -- [15:12] == 0 */
+#define CPU_ID_ARM3		0x41560300
+#define CPU_ID_ARM600		0x41560600
+#define CPU_ID_ARM610		0x41560610
+#define CPU_ID_ARM620		0x41560620
+
+/* ARM7 CPUs -- [15:12] == 7 */
+#define CPU_ID_ARM710		0x41007100
+#define CPU_ID_ARM7100		0x41047100
+#define CPU_ID_ARM710T		0x41807100
+#define CPU_ID_ARM720T		0x41807200
+#define CPU_ID_ARM740T8K	0x41807400 /* XXX no MMU, 8KB cache */
+#define CPU_ID_ARM740T4K	0x41817400 /* XXX no MMU, 4KB cache */
+
+/* Post-ARM7 CPUs */
+#define CPU_ID_ARM810		0x41018100
+#define CPU_ID_ARM920T		0x41129200
+#define CPU_ID_ARM922T		0x41029220
+#define CPU_ID_ARM940T		0x41029400 /* XXX no MMU */
+#define CPU_ID_ARM946ES		0x41049460 /* XXX no MMU */
+#define	CPU_ID_ARM966ES		0x41049660 /* XXX no MMU */
+#define	CPU_ID_ARM966ESR1	0x41059660 /* XXX no MMU */
+#define CPU_ID_SA110		0x4401a100
+#define CPU_ID_SA1100		0x4401a110
+#define CPU_ID_SA1110		0x6901b110
+#define CPU_ID_I80200		0x69052000 /* XScale core */
+
+#define CPU_ID_ARM700		0x00007000
+
+/* ARM3-specific coprocessor 15 registers */
+#define ARM3_CP15_FLUSH		1
+#define ARM3_CP15_CONTROL	2
+#define ARM3_CP15_CACHEABLE	3
+#define ARM3_CP15_UPDATEABLE	4
+#define ARM3_CP15_DISRUPTIVE	5	
+
+/* ARM3 Control register bits */
+#define ARM3_CTL_CACHE_ON	0x00000001
+#define ARM3_CTL_SHARED		0x00000002
+#define ARM3_CTL_MONITOR	0x00000004
+
+/*
+ * Post-ARM3 CP15 registers:
+ */
+/* Some of the definitions below need cleaning up for V3/V4 architectures */
+
+/* CPU control register (CP15 register 1) */
+#define CPU_CONTROL_MMU_ENABLE	0x00000001 /* M: MMU/Protection unit enable */
+#define CPU_CONTROL_AFLT_ENABLE	0x00000002 /* A: Alignment fault enable */
+#define CPU_CONTROL_DC_ENABLE	0x00000004 /* C: IDC/DC enable */
+#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */
+#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */
+#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */
+#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */
+#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */
+#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */
+#define CPU_CONTROL_ROM_ENABLE	0x00000200 /* R: ROM protection bit */
+#define CPU_CONTROL_CPCLK	0x00000400 /* F: Implementation defined */
+#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */
+#define CPU_CONTROL_IC_ENABLE   0x00001000 /* I: IC enable */
+#define CPU_CONTROL_VECRELOC	0x00002000 /* V: Vector relocation */
+#define CPU_CONTROL_ROUNDROBIN	0x00004000 /* RR: Predictable replacement */
+#define CPU_CONTROL_V4COMPAT	0x00008000 /* L4: ARMv4 compat LDR R15 etc */
+
+#define CPU_CONTROL_IDC_ENABLE	CPU_CONTROL_DC_ENABLE
+
+/* Cache type register definitions */
+#define CPU_CT_IINFO_MASK	0x00000fff
+#define CPU_CT_IINFO_SHIFT	0
+#define CPU_CT_DINFO_MASK	0x00fff000
+#define CPU_CT_DINFO_SHIFT	12
+#define CPU_CT_HARVARD		0x01000000
+#define CPU_CT_TYPE_MASK	0x1e000000
+/* "Info" subfields -- see ARM ARM for meanings. */
+#define CPU_CT_LINE_MASK	0x00000003
+#define CPU_CT_M_BIT		0x00000004
+#define CPU_CT_ASSOC_MASK	0x00000038
+#define CPU_CT_SIZE_MASK	0x000001c0
+
+/* Fault status register definitions */
+
+#define FAULT_TYPE_MASK 0x0f
+#define FAULT_USER      0x10
+
+#define FAULT_WRTBUF_0  0x00 /* Vector Exception */
+#define FAULT_WRTBUF_1  0x02 /* Terminal Exception */
+#define FAULT_BUSERR_0  0x04 /* External Abort on Linefetch -- Section */
+#define FAULT_BUSERR_1  0x06 /* External Abort on Linefetch -- Page */
+#define FAULT_BUSERR_2  0x08 /* External Abort on Non-linefetch -- Section */
+#define FAULT_BUSERR_3  0x0a /* External Abort on Non-linefetch -- Page */
+#define FAULT_BUSTRNL1  0x0c /* External abort on Translation -- Level 1 */
+#define FAULT_BUSTRNL2  0x0e /* External abort on Translation -- Level 2 */
+#define FAULT_ALIGN_0   0x01 /* Alignment */
+#define FAULT_ALIGN_1   0x03 /* Alignment */
+#define FAULT_TRANS_S   0x05 /* Translation -- Section */
+#define FAULT_TRANS_P   0x07 /* Translation -- Page */
+#define FAULT_DOMAIN_S  0x09 /* Domain -- Section */
+#define FAULT_DOMAIN_P  0x0b /* Domain -- Page */
+#define FAULT_PERM_S    0x0d /* Permission -- Section */
+#define FAULT_PERM_P    0x0f /* Permission -- Page */
+
+/*
+ * ARM Instructions
+ *
+ *       3 3 2 2 2                              
+ *       1 0 9 8 7                                                     0
+ *      +-------+-------------------------------------------------------+
+ *      | cond  |              instruction dependant                    |
+ *      |c c c c|                                                       |
+ *      +-------+-------------------------------------------------------+
+ */
+
+#define INSN_SIZE		4		/* Always 4 bytes */
+#define INSN_COND_MASK		0xf0000000	/* Condition mask */
+#define INSN_COND_AL		0xe0000000	/* Always condition */
+
+#endif
diff --git a/sys/arch/arm26/arm26/cpu.c b/sys/arch/arm26/arm26/cpu.c
index 0a6e7a537f73..5f764d226ac4 100644
--- a/sys/arch/arm26/arm26/cpu.c
+++ b/sys/arch/arm26/arm26/cpu.c
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.3 2000/12/23 13:37:03 bjh21 Exp $ */
+/* $NetBSD: cpu.c,v 1.4 2001/01/22 22:10:41 bjh21 Exp $ */
 
 /*-
  * Copyright (c) 2000 Ben Harris
@@ -33,14 +33,14 @@
 
 #include <sys/param.h>
 
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.3 2000/12/23 13:37:03 bjh21 Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.4 2001/01/22 22:10:41 bjh21 Exp $");
 
 #include <sys/device.h>
 #include <sys/proc.h>
 #include <sys/systm.h>
 #include <sys/time.h>
 #include <sys/user.h>
-#include <machine/armreg.h>
+#include <arm/armreg.h>
 #include <machine/machdep.h>
 #include <machine/pcb.h>
 
diff --git a/sys/arch/arm26/arm26/db_trace.c b/sys/arch/arm26/arm26/db_trace.c
index c48e06143282..8d6a3e9abed9 100644
--- a/sys/arch/arm26/arm26/db_trace.c
+++ b/sys/arch/arm26/arm26/db_trace.c
@@ -1,4 +1,4 @@
-/*	$NetBSD: db_trace.c,v 1.5 2001/01/18 17:05:06 bjh21 Exp $	*/
+/*	$NetBSD: db_trace.c,v 1.6 2001/01/22 22:10:42 bjh21 Exp $	*/
 
 /* 
  * Copyright (c) 1996 Scott K. Stevens
@@ -29,9 +29,12 @@
  */
 
 #include <sys/param.h>
+
+__RCSID("$NetBSD: db_trace.c,v 1.6 2001/01/22 22:10:42 bjh21 Exp $");
+
 #include <sys/proc.h>
 #include <sys/user.h>
-#include <machine/armreg.h>
+#include <arm/armreg.h>
 #include <machine/db_machdep.h>
 
 #include <ddb/db_access.h>
diff --git a/sys/arch/arm26/arm26/except.c b/sys/arch/arm26/arm26/except.c
index 95097a79bde5..6b0b839b934a 100644
--- a/sys/arch/arm26/arm26/except.c
+++ b/sys/arch/arm26/arm26/except.c
@@ -1,4 +1,4 @@
-/* $NetBSD: except.c,v 1.25 2001/01/20 17:14:20 bjh21 Exp $ */
+/* $NetBSD: except.c,v 1.26 2001/01/22 22:10:42 bjh21 Exp $ */
 /*-
  * Copyright (c) 1998, 1999, 2000 Ben Harris
  * All rights reserved.
@@ -32,7 +32,7 @@
 
 #include <sys/param.h>
 
-__KERNEL_RCSID(0, "$NetBSD: except.c,v 1.25 2001/01/20 17:14:20 bjh21 Exp $");
+__KERNEL_RCSID(0, "$NetBSD: except.c,v 1.26 2001/01/22 22:10:42 bjh21 Exp $");
 
 #include "opt_cputypes.h"
 #include "opt_ddb.h"
@@ -48,7 +48,7 @@ __KERNEL_RCSID(0, "$NetBSD: except.c,v 1.25 2001/01/20 17:14:20 bjh21 Exp $");
 
 #include <uvm/uvm_extern.h>
 
-#include <machine/armreg.h>
+#include <arm/armreg.h>
 #include <machine/intr.h>
 #include <machine/machdep.h>
 #include <machine/pcb.h>
diff --git a/sys/arch/arm26/arm26/locore.S b/sys/arch/arm26/arm26/locore.S
index ee3d54cde01a..c65974b8be2e 100644
--- a/sys/arch/arm26/arm26/locore.S
+++ b/sys/arch/arm26/arm26/locore.S
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.10 2001/01/20 17:14:20 bjh21 Exp $ */
+/* $NetBSD: locore.S,v 1.11 2001/01/22 22:10:43 bjh21 Exp $ */
 /*
  * Copyright (c) 1998, 1999, 2000 Ben Harris
  * Copyright (C) 1994-1997 Mark Brinicombe
@@ -41,7 +41,7 @@
 /* RCSID is at the end of the file in case it gets put in the text segment. */
 
 #include <sys/syscall.h>
-#include <machine/armreg.h>
+#include <arm/armreg.h>
 #include "assym.h"
 
 #include "opt_cputypes.h"
@@ -456,4 +456,4 @@ _C_LABEL(intrcnt):
 	.global	_C_LABEL(eintrcnt)
 _C_LABEL(eintrcnt):
 
-RCSID("$NetBSD: locore.S,v 1.10 2001/01/20 17:14:20 bjh21 Exp $")
+RCSID("$NetBSD: locore.S,v 1.11 2001/01/22 22:10:43 bjh21 Exp $")
diff --git a/sys/arch/arm26/arm26/process_machdep.c b/sys/arch/arm26/arm26/process_machdep.c
index bbbee786043f..a4c2bd4d5196 100644
--- a/sys/arch/arm26/arm26/process_machdep.c
+++ b/sys/arch/arm26/arm26/process_machdep.c
@@ -1,4 +1,4 @@
-/* $NetBSD: process_machdep.c,v 1.1 2000/08/20 15:16:51 bjh21 Exp $ */
+/* $NetBSD: process_machdep.c,v 1.2 2001/01/22 22:10:43 bjh21 Exp $ */
 /*-
  * Copyright (c) 2000 Ben Harris
  * All rights reserved.
@@ -32,14 +32,14 @@
 
 #include <sys/param.h>
 
-__RCSID("$NetBSD: process_machdep.c,v 1.1 2000/08/20 15:16:51 bjh21 Exp $");
+__RCSID("$NetBSD: process_machdep.c,v 1.2 2001/01/22 22:10:43 bjh21 Exp $");
 
 #include <sys/errno.h>
 #include <sys/proc.h>
 #include <sys/ptrace.h>
 #include <sys/user.h>
 
-#include <machine/armreg.h>
+#include <arm/armreg.h>
 #include <machine/frame.h>
 #include <machine/pcb.h>
 #include <machine/reg.h>
diff --git a/sys/arch/arm26/arm26/start.c b/sys/arch/arm26/arm26/start.c
index 52baf957e8dc..132a87cd5d75 100644
--- a/sys/arch/arm26/arm26/start.c
+++ b/sys/arch/arm26/arm26/start.c
@@ -1,4 +1,4 @@
-/* $NetBSD: start.c,v 1.7 2000/12/27 20:43:44 bjh21 Exp $ */
+/* $NetBSD: start.c,v 1.8 2001/01/22 22:10:43 bjh21 Exp $ */
 /*-
  * Copyright (c) 1998, 2000 Ben Harris
  * All rights reserved.
@@ -32,14 +32,14 @@
 
 #include <sys/param.h>
 
-__KERNEL_RCSID(0, "$NetBSD: start.c,v 1.7 2000/12/27 20:43:44 bjh21 Exp $");
+__KERNEL_RCSID(0, "$NetBSD: start.c,v 1.8 2001/01/22 22:10:43 bjh21 Exp $");
 
 #include <sys/msgbuf.h>
 #include <sys/user.h>
 #include <sys/syslog.h>
 #include <sys/systm.h>
 
-#include <machine/armreg.h>
+#include <arm/armreg.h>
 #include <machine/boot.h>
 #include <machine/machdep.h>
 #include <machine/memcreg.h>
diff --git a/sys/arch/arm26/arm26/vm_machdep.c b/sys/arch/arm26/arm26/vm_machdep.c
index 4631d804ea37..a24c3f372073 100644
--- a/sys/arch/arm26/arm26/vm_machdep.c
+++ b/sys/arch/arm26/arm26/vm_machdep.c
@@ -1,4 +1,4 @@
-/* $NetBSD: vm_machdep.c,v 1.10 2001/01/16 00:29:45 bjh21 Exp $ */
+/* $NetBSD: vm_machdep.c,v 1.11 2001/01/22 22:10:44 bjh21 Exp $ */
 
 /*-
  * Copyright (c) 2000, 2001 Ben Harris
@@ -66,7 +66,7 @@
 
 #include <sys/param.h>
 
-__RCSID("$NetBSD: vm_machdep.c,v 1.10 2001/01/16 00:29:45 bjh21 Exp $");
+__RCSID("$NetBSD: vm_machdep.c,v 1.11 2001/01/22 22:10:44 bjh21 Exp $");
 
 #include <sys/buf.h>
 #include <sys/exec.h>
@@ -77,7 +77,7 @@ __RCSID("$NetBSD: vm_machdep.c,v 1.10 2001/01/16 00:29:45 bjh21 Exp $");
 
 #include <uvm/uvm_extern.h>
 
-#include <machine/armreg.h>
+#include <arm/armreg.h>
 #include <machine/frame.h>
 #include <machine/intr.h>
 #include <machine/machdep.h>
diff --git a/sys/arch/arm26/include/Makefile b/sys/arch/arm26/include/Makefile
index 9d913c03b355..a2d8312d3a27 100644
--- a/sys/arch/arm26/include/Makefile
+++ b/sys/arch/arm26/include/Makefile
@@ -1,9 +1,9 @@
-#	$NetBSD: Makefile,v 1.3 2000/08/22 21:27:21 bjh21 Exp $
+#	$NetBSD: Makefile,v 1.4 2001/01/22 22:10:44 bjh21 Exp $
 
 KDIR=	/sys/arch/arm26/include
 INCSDIR= /usr/include/arm26
 
-INCS=	ansi.h aout_machdep.h armreg.h asm.h boot.h bswap.h bus.h cdefs.h \
+INCS=	ansi.h aout_machdep.h asm.h boot.h bswap.h bus.h cdefs.h \
 	cpu.h db_machdep.h disklabel.h \
 	disklabel_acorn.h elf_machdep.h endian.h endian_machdep.h float.h \
 	fp.h frame.h ieee.h ieeefp.h int_types.h intr.h ipkdb.h irq.h \
diff --git a/sys/arch/arm26/include/armreg.h b/sys/arch/arm26/include/armreg.h
deleted file mode 100644
index d6f7bf893bed..000000000000
--- a/sys/arch/arm26/include/armreg.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* $NetBSD: armreg.h,v 1.1 2000/05/09 21:55:58 bjh21 Exp $ */
-/*-
- * Copyright (c) 1998 Ben Harris
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-/* This file is part of NetBSD/arm26 -- a port of NetBSD to ARM2/3 machines. */
-
-#ifndef _ARM26_ARMREG_H
-#define _ARM26_ARMREG_H
-
-/* All the junk the old ARMs stuff in R15 */
-
-#define R15_MODE	0x00000003
-#define R15_MODE_USR	0x00000000
-#define R15_MODE_FIQ	0x00000001
-#define R15_MODE_IRQ	0x00000002
-#define R15_MODE_SVC	0x00000003
-
-#define R15_PC		0x03fffffc
-
-#define R15_FIQ_DISABLE	0x04000000
-#define R15_IRQ_DISABLE	0x08000000
-
-#define R15_FLAGS	0xf0000000
-#define R15_FLAG_N	0x80000000
-#define R15_FLAG_Z	0x40000000
-#define R15_FLAG_C	0x20000000
-#define R15_FLAG_V	0x10000000
-
-#define ARM_CP15_CPU_ID		0
-
-/* Not really many CPUs to consider */
-#define CPU_ID_DESIGNER_MASK	0xff000000
-#define CPU_ID_ARM_LTD		0x41000000
-#define CPU_ID_TYPE_MASK	0x00ff0000
-#define CPU_ID_ARM		0x00560000
-#define CPU_ID_CPU_MASK		0x0000fff0
-#define CPU_ID_ARM3		0x00000300
-#define CPU_ID_REVISION_MASK	0x0000000f
-
-/* Fake CPU IDs for older ARMs */
-#define CPU_ID_ARM2	0x00000200
-#define CPU_ID_ARM250	0x00000250
-
-/* ARM3-specific coprocessor 15 register */
-#define ARM3_CP15_FLUSH		1
-#define ARM3_CP15_CONTROL	2
-#define ARM3_CP15_CACHEABLE	3
-#define ARM3_CP15_UPDATEABLE	4
-#define ARM3_CP15_DISRUPTIVE	5	
-
-/* Control register bits */
-#define ARM3_CTL_CACHE_ON	1
-#define ARM3_CTL_SHARED		2
-#define ARM3_CTL_MONITOR	4
-
-#endif
diff --git a/sys/arch/arm26/include/db_machdep.h b/sys/arch/arm26/include/db_machdep.h
index 17224a1bb380..a934fe5f4dc9 100644
--- a/sys/arch/arm26/include/db_machdep.h
+++ b/sys/arch/arm26/include/db_machdep.h
@@ -1,4 +1,4 @@
-/* $NetBSD: db_machdep.h,v 1.3 2000/12/10 01:31:48 bjh21 Exp $ */
+/* $NetBSD: db_machdep.h,v 1.4 2001/01/22 22:10:45 bjh21 Exp $ */
 
 /*
  * Copyright (c) 1996 Scott K Stevens
@@ -36,7 +36,7 @@
  */
 
 #include <uvm/uvm_extern.h>
-#include <machine/armreg.h>
+#include <arm/armreg.h>
 #include <machine/frame.h>
 
 typedef	vm_offset_t	db_addr_t;	/* address - unsigned */
diff --git a/sys/arch/arm26/include/frame.h b/sys/arch/arm26/include/frame.h
index 1e37ee29a718..ae34c200a532 100644
--- a/sys/arch/arm26/include/frame.h
+++ b/sys/arch/arm26/include/frame.h
@@ -1,4 +1,4 @@
-/*	$NetBSD: frame.h,v 1.4 2001/01/20 17:14:20 bjh21 Exp $	*/
+/*	$NetBSD: frame.h,v 1.5 2001/01/22 22:10:46 bjh21 Exp $	*/
 
 /*
  * Copyright (c) 1999 Ben Harris.
@@ -46,7 +46,7 @@
 
 #ifndef _LOCORE
 
-#include <machine/armreg.h>
+#include <arm/armreg.h>
 
 /*
  * System stack frames.