* Only FFS is needed for the install kernel.
* Configure the console to 8N1 (that's what the pc532's rom monitor uses).
* The install kernel doesn't need to know about CDROM drives.
* Use the new mi ramdisk.
setrunqueue(), but remrq() was never renamed. Rename remrq() to
remrunqueue(). Also, move remrunqueue() prototype from vm/vm_extern.h
to sys/proc.h, so that it's in the same place as the setrunqueue() prototype
and other related prototypes.
the wrong thing with standby mode (as some older ThinkPAD 701c BIOSes do, for
example.) Rename APM_NOIDLE to APM_NO_IDLE for consistency and "niceness,"
and error out (with a useful error message) if APM_NOIDLE is defined.
floppy driver.
- Fixup format types in the debug-printf's
- Don't print empty lines on unconfigured drives.
- When a drive is detected, show it's default format.
---- Warning: minor numbers are shifted! ---
ISA-compatible port space of PCI buslogic cards.
* Add call to bha_pci.c to disable the ISA-compatible ports of a PCI
device. The ISA-compatible ports are enabled by default, which
causes the card to be autoconfigured a second time as an ISA device,
which appears to deadlock the card.
* Change bha_cmd() to return the number of bytes it actually received
in response to a command, or -1 on error.
* Use heuristics (checking for bha-only registers, and checking the size
of the response to BHA_INQURE_EXTENDED) to bha_find, to make sure the
bha driver never matches an aha (Adaptec 1542 or compatible) device.
A single kernel should now boot on either Adaptec or BusLogic controllers,
provided we always probe for BusLogic devices before Adaptec devices,
but this has not yet been verified.
instead of 0x400.
- Restructure interrupt handling for more performance--continue to
read/write data as long as the device keeps us in a data xfer phase.
There is still a lot of room for speed improvement here. Perhaps it
lies is speeding up the interrupt path in general?
naming for fmovem, while breaking it for fmove. We probably never will
see normal fmove in the kernel, nevertheless it should be corrected while
somebody remembers.
Besides, the correct patch is smaller and thus easier to verify than the
origininal one.
Added support the new instructions defined in the ARM V4 Architecture
Reference manual (long multiplies, half word load and stores,
half word/byte signed loads).
Added support for the ARM810 IMB architecture defined SWIs.
Fixed bug in calculating some immediate constants.
Added support for the wfs, rfs, wfc, rfc instructions
Added support for the floating point compare instructions
Added ldf, stf, ldc and stc instructions.
Fixed mis-disassembly of some msr/mrs instructions.
The ldm and stm instructions will modify the direction identifier to
use the stack variations if the base register is r13.
variant of the CG4 (the one with the AMD colormap DACs). This has
been tested only on the "Type B" H/W at this point (Brooktree DACs).
Thanks to Ezra Story and Scott Ellis for the "Type A" support.
some guesses for the machines that have two of these buggers (I don't have
such a machine). This driver is a copy of the sparc/alpha esp with a
minimum of changes--after we get it performing a bit more respectably,
we should see about re-normalizing the sources.
- add a missing return; at the end of a case, leading to wrong disassembly
of the next few instructions after fmovem.
- while we're here, correct the same bug in PBcc.
XXX there are a few other dubious fallthroughs in this file (which are
not explicitly marked with /* FALLTHROUGH */), which I didn't yet analyze.
* Fix other FMOVEM interpretation bugs:
- correct printing of FP data register lists if all are used (only FP0
would be mentioned)
- correct printing of FP data register lists in the case the list is reversed
(would have printed nothing)
- correct mapping of fp0-fp7 to register list bits (was reversed)
- correct printing of FP control register lists (this list is never reversed)
- correct printing of FMOVEM with FP control registers (the data direction
was interpreted the wrong way)
* While we're here, enhance the comments in MOVC's list of cpu control
registers
second on Sun4m machines. Although this was in the noise of the unstable
Sun clock crystals before, the discrepancy amounted to about 100 ppm, and
thus made NTP perform poorly. NTP now works happily on my SS20...
matthias