* Fix a few wrong fallthroughs in switch cases:
- add a missing return; at the end of a case, leading to wrong disassembly of the next few instructions after fmovem. - while we're here, correct the same bug in PBcc. XXX there are a few other dubious fallthroughs in this file (which are not explicitly marked with /* FALLTHROUGH */), which I didn't yet analyze. * Fix other FMOVEM interpretation bugs: - correct printing of FP data register lists if all are used (only FP0 would be mentioned) - correct printing of FP data register lists in the case the list is reversed (would have printed nothing) - correct mapping of fp0-fp7 to register list bits (was reversed) - correct printing of FP control register lists (this list is never reversed) - correct printing of FMOVEM with FP control registers (the data direction was interpreted the wrong way) * While we're here, enhance the comments in MOVC's list of cpu control registers
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072b7020c4
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@ -1,4 +1,4 @@
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/* $NetBSD: db_disasm.c,v 1.16 1996/10/24 18:30:17 is Exp $ */
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/* $NetBSD: db_disasm.c,v 1.17 1996/10/28 08:43:18 is Exp $ */
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/*
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* Copyright (c) 1994 Christian E. Hopps
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@ -152,7 +152,7 @@ const char *const mmcc_table[16] = {
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const char *const aregs[8] = {"a0","a1","a2","a3","a4","a5","a6","sp"};
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const char *const dregs[8] = {"d0","d1","d2","d3","d4","d5","d6","d7"};
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const char *const fpregs[8] = {
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"fp0","fp1","fp2","fp3","fp4","fp5","fp6","fp7" };
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"fp7","fp6","fp5","fp4","fp3","fp2","fp1","fp0" };
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const char *const fpcregs[3] = { "fpiar", "fpsr", "fpcr" };
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/*
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@ -1383,6 +1383,7 @@ opcode_fpu(dbuf, opc)
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}
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if (ISBITSET(ext,15) || ISBITSET(ext,13)) {
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opcode_fmove_ext(dbuf, opc, ext);
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return;
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}
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switch(opmode) {
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@ -1637,12 +1638,12 @@ opcode_fmove_ext(dbuf, opc, ext)
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addchar('l');
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addchar('\t');
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if (!ISBITSET(ext,13)) {
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if (ISBITSET(ext,13)) {
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print_freglist(dbuf, AR_DEC, BITFIELD(ext,12,10), 1);
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addchar(',');
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}
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get_modregstr(dbuf, 5, GETMOD_BEFORE, SIZE_LONG, 1);
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if (ISBITSET(ext,13)) {
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if (!ISBITSET(ext,13)) {
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addchar(',');
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print_freglist(dbuf, AR_DEC, BITFIELD(ext,12,10), 1);
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}
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@ -1736,6 +1737,7 @@ opcode_mmu(dbuf, opc)
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-1);
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dbuf->used += 2;
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}
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return;
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case 1:
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ext = *(dbuf->val + 1);
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dbuf->used++;
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@ -2105,19 +2107,22 @@ print_freglist(dbuf, mod, rl, cntl)
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regs = cntl ? fpcregs : fpregs;
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upper = cntl ? 3 : 8;
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if (mod == AR_DEC) {
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if (!cntl && mod == AR_DEC) {
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list = rl;
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rl = 0;
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/* I am sure there is some trick... */
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for (bit = 0; bit < upper; bit++)
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if (list & (1 << bit))
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rl |= (0x8000 >> bit);
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rl |= 1 << (upper-bit-1);
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}
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for (bit = 0, list = 0; bit < upper; bit++) {
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for (bit = upper-1, list = 0; bit >= 0; bit--) {
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if (ISBITSET(rl,bit)) {
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if (list == 0) {
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list = 1;
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addstr(dbuf, regs[bit]);
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if (cntl)
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addchar('/');
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else
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list = 1;
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} else if (list == 1) {
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list++;
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addchar('-');
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@ -2125,12 +2130,15 @@ print_freglist(dbuf, mod, rl, cntl)
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} else {
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if (list) {
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if (list > 1)
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addstr(dbuf, regs[bit-1]);
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addstr(dbuf, regs[bit+1]);
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addchar('/');
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list = 0;
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}
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}
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}
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if (list > 1)
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addstr(dbuf, regs[0]);
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if (dbuf->casm[-1] == '/' || dbuf->casm[-1] == '-')
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dbuf->casm--;
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*dbuf->casm = 0;
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@ -2189,7 +2197,7 @@ opcode_movec(dbuf, opc)
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addchar(',');
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}
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switch (BITFIELD(ext,11,0)) {
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/* 010/020/030/040/CPU32 */
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/* 010/020/030/040/CPU32/060 */
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case 0x000:
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tmp = "sfc";
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break;
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@ -2206,17 +2214,18 @@ opcode_movec(dbuf, opc)
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case 0x802:
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tmp = "caar";
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break;
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/* 020/030/040 */
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/* 020/030/040/060 */
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case 0x002:
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tmp = "cacr";
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break;
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/* 020/030/040 */
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case 0x803:
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tmp = "msp";
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break;
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case 0x804:
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tmp = "isp";
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break;
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/* 040 */
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/* 040/060 */
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case 0x003:
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tmp = "tc";
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break;
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@ -2232,16 +2241,18 @@ opcode_movec(dbuf, opc)
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case 0x007:
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tmp = "dtt1";
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break;
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/* 040 */
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case 0x805:
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tmp = "mmusr";
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break;
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/* 040/060 */
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case 0x806:
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tmp = "urp";
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break;
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case 0x807:
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tmp = "srp";
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break;
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/* 060: */
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/* 060 */
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case 0x808:
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tmp = "pcr";
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break;
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