Interrupt-driven, but slow, NCR 53c96 driver for the 040-based macs. Contains
some guesses for the machines that have two of these buggers (I don't have such a machine). This driver is a copy of the sparc/alpha esp with a minimum of changes--after we get it performing a bit more respectably, we should see about re-normalizing the sources.
This commit is contained in:
briggs
parent
d7578a89cf
commit
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/* $NetBSD: espreg.h,v 1.1 1996/10/29 06:08:59 briggs Exp $ */
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/*
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* Copyright (c) 1994 Peter Galbavy. All rights reserved.
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
|
||||
* are met:
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
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||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
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||||
* 3. All advertising materials mentioning features or use of this software
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||||
* must display the following acknowledgement:
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* This product includes software developed by Peter Galbavy.
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* 4. The name of the author may not be used to endorse or promote products
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||||
* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Register addresses, relative to some base address
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*/
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#define ESP_TCL 0x00 /* RW - Transfer Count Low */
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#define ESP_TCM 0x01 /* RW - Transfer Count Mid */
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#define ESP_TCH 0x0e /* RW - Transfer Count High */
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/* NOT on 53C90 */
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#define ESP_FIFO 0x02 /* RW - FIFO data */
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#define ESP_CMD 0x03 /* RW - Command (2 deep) */
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#define ESPCMD_DMA 0x80 /* DMA Bit */
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#define ESPCMD_NOP 0x00 /* No Operation */
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#define ESPCMD_FLUSH 0x01 /* Flush FIFO */
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#define ESPCMD_RSTCHIP 0x02 /* Reset Chip */
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#define ESPCMD_RSTSCSI 0x03 /* Reset SCSI Bus */
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#define ESPCMD_RESEL 0x40 /* Reselect Sequence */
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#define ESPCMD_SELNATN 0x41 /* Select without ATN */
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#define ESPCMD_SELATN 0x42 /* Select with ATN */
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#define ESPCMD_SELATNS 0x43 /* Select with ATN & Stop */
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#define ESPCMD_ENSEL 0x44 /* Enable (Re)Selection */
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#define ESPCMD_DISSEL 0x45 /* Disable (Re)Selection */
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#define ESPCMD_SELATN3 0x46 /* Select with ATN3 */
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#define ESPCMD_RESEL3 0x47 /* Reselect3 Sequence */
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#define ESPCMD_SNDMSG 0x20 /* Send Message */
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#define ESPCMD_SNDSTAT 0x21 /* Send Status */
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#define ESPCMD_SNDDATA 0x22 /* Send Data */
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#define ESPCMD_DISCSEQ 0x23 /* Disconnect Sequence */
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#define ESPCMD_TERMSEQ 0x24 /* Terminate Sequence */
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#define ESPCMD_TCCS 0x25 /* Target Command Comp Seq */
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#define ESPCMD_DISC 0x27 /* Disconnect */
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#define ESPCMD_RECMSG 0x28 /* Receive Message */
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#define ESPCMD_RECCMD 0x29 /* Receive Command */
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#define ESPCMD_RECDATA 0x2a /* Receive Data */
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#define ESPCMD_RECCSEQ 0x2b /* Receive Command Sequence*/
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#define ESPCMD_ABORT 0x04 /* Target Abort DMA */
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#define ESPCMD_TRANS 0x10 /* Transfer Information */
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#define ESPCMD_ICCS 0x11 /* Initiator Cmd Comp Seq */
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#define ESPCMD_MSGOK 0x12 /* Message Accepted */
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#define ESPCMD_TRPAD 0x18 /* Transfer Pad */
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#define ESPCMD_SETATN 0x1a /* Set ATN */
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#define ESPCMD_RSTATN 0x1b /* Reset ATN */
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#define ESP_STAT 0x04 /* RO - Status */
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#define ESPSTAT_INT 0x80 /* Interrupt */
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#define ESPSTAT_GE 0x40 /* Gross Error */
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#define ESPSTAT_PE 0x20 /* Parity Error */
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#define ESPSTAT_TC 0x10 /* Terminal Count */
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#define ESPSTAT_VGC 0x08 /* Valid Group Code */
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#define ESPSTAT_PHASE 0x07 /* Phase bits */
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#define ESP_SELID 0x04 /* WO - Select/Reselect Bus ID */
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#define ESP_INTR 0x05 /* RO - Interrupt */
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#define ESPINTR_SBR 0x80 /* SCSI Bus Reset */
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#define ESPINTR_ILL 0x40 /* Illegal Command */
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#define ESPINTR_DIS 0x20 /* Disconnect */
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#define ESPINTR_BS 0x10 /* Bus Service */
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#define ESPINTR_FC 0x08 /* Function Complete */
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#define ESPINTR_RESEL 0x04 /* Reselected */
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#define ESPINTR_SELATN 0x02 /* Select with ATN */
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#define ESPINTR_SEL 0x01 /* Selected */
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#define ESP_TIMEOUT 0x05 /* WO - Select/Reselect Timeout */
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#define ESP_STEP 0x06 /* RO - Sequence Step */
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#define ESPSTEP_MASK 0x07 /* the last 3 bits */
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#define ESPSTEP_DONE 0x04 /* command went out */
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#define ESP_SYNCTP 0x06 /* WO - Synch Transfer Period */
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/* Default 5 (53C9X) */
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#define ESP_FFLAG 0x07 /* RO - FIFO Flags */
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#define ESPFIFO_SS 0xe0 /* Sequence Step (Dup) */
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#define ESPFIFO_FF 0x1f /* Bytes in FIFO */
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#define ESP_SYNCOFF 0x07 /* WO - Synch Offset */
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/* 0 = ASYNC */
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/* 1 - 15 = SYNC bytes */
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#define ESP_CFG1 0x08 /* RW - Configuration #1 */
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#define ESPCFG1_SLOW 0x80 /* Slow Cable Mode */
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#define ESPCFG1_SRR 0x40 /* SCSI Reset Rep Int Dis */
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#define ESPCFG1_PTEST 0x20 /* Parity Test Mod */
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#define ESPCFG1_PARENB 0x10 /* Enable Parity Check */
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#define ESPCFG1_CTEST 0x08 /* Enable Chip Test */
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#define ESPCFG1_BUSID 0x07 /* Bus ID */
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#define ESP_CCF 0x09 /* WO - Clock Conversion Factor */
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/* 0 = 35.01 - 40Mhz */
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/* NEVER SET TO 1 */
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/* 2 = 10Mhz */
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/* 3 = 10.01 - 15Mhz */
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/* 4 = 15.01 - 20Mhz */
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/* 5 = 20.01 - 25Mhz */
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/* 6 = 25.01 - 30Mhz */
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/* 7 = 30.01 - 35Mhz */
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#define ESP_TEST 0x0a /* WO - Test (Chip Test Only) */
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#define ESP_CFG2 0x0b /* RW - Configuration #2 */
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#define ESPCFG2_RSVD 0xa0 /* reserved */
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#define ESPCFG2_FE 0x40 /* Features Enable */
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#define ESPCFG2_DREQ 0x10 /* DREQ High Impedance */
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#define ESPCFG2_SCSI2 0x08 /* SCSI-2 Enable */
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#define ESPCFG2_BPA 0x04 /* Target Bad Parity Abort */
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#define ESPCFG2_RPE 0x02 /* Register Parity Error */
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#define ESPCFG2_DPE 0x01 /* DMA Parity Error */
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/* Config #3 only on 53C9X */
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#define ESP_CFG3 0x0c /* RW - Configuration #3 */
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#define ESPCFG3_RSVD 0xe0 /* reserved */
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#define ESPCFG3_IDM 0x10 /* ID Message Res Check */
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#define ESPCFG3_QTE 0x08 /* Queue Tag Enable */
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#define ESPCFG3_CDB 0x04 /* CDB 10-bytes OK */
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#define ESPCFG3_FSCSI 0x02 /* Fast SCSI */
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#define ESPCFG3_FCLK 0x01 /* Fast Clock (>25Mhz) */
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@ -0,0 +1,391 @@
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/* $NetBSD: espvar.h,v 1.1 1996/10/29 06:09:00 briggs Exp $ */
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/*
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* Copyright (c) 1994 Peter Galbavy. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
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||||
* 2. Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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||||
* must display the following acknowledgement:
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* This product includes software developed by Peter Galbavy.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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||||
*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <machine/param.h>
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#if defined(__sparc__) && !defined(SPARC_DRIVER)
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#define SPARC_DRIVER
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#else
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#if (_MACHINE == mac68k) && !defined(MAC68K_DRIVER)
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#define MAC68K_DRIVER
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#endif
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#endif
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#define ESP_DEBUG 0
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#define ESP_ABORT_TIMEOUT 2000 /* time to wait for abort */
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#define FREQTOCCF(freq) (((freq + 4) / 5))
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/* esp revisions */
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#define ESP100 0x01
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#define ESP100A 0x02
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#define ESP200 0x03
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#define NCR53C94 0x04
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#define NCR53C96 0x05
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/*
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* ECB. Holds additional information for each SCSI command Comments: We
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* need a separate scsi command block because we may need to overwrite it
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* with a request sense command. Basicly, we refrain from fiddling with
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* the scsi_xfer struct (except do the expected updating of return values).
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* We'll generally update: xs->{flags,resid,error,sense,status} and
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* occasionally xs->retries.
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*/
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struct esp_ecb {
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TAILQ_ENTRY(esp_ecb) chain;
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struct scsi_xfer *xs; /* SCSI xfer ctrl block from above */
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int flags;
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#define ECB_ALLOC 0x01
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#define ECB_NEXUS 0x02
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#define ECB_SENSE 0x04
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#define ECB_ABORT 0x40
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#define ECB_RESET 0x80
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int timeout;
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struct scsi_generic cmd; /* SCSI command block */
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int clen;
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char *daddr; /* Saved data pointer */
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int dleft; /* Residue */
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u_char stat; /* SCSI status byte */
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#if ESP_DEBUG > 0
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char trace[1000];
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#endif
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};
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#if ESP_DEBUG > 0
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#define ECB_TRACE(ecb, msg, a, b) do { \
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const char *f = "[" msg "]"; \
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int n = strlen((ecb)->trace); \
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if (n < (sizeof((ecb)->trace)-100)) \
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sprintf((ecb)->trace + n, f, a, b); \
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} while(0)
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#else
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#define ECB_TRACE(ecb, msg, a, b)
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#endif
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/*
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* Some info about each (possible) target on the SCSI bus. This should
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* probably have been a "per target+lunit" structure, but we'll leave it at
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* this for now. Is there a way to reliably hook it up to sc->fordriver??
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*/
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struct esp_tinfo {
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int cmds; /* #commands processed */
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int dconns; /* #disconnects */
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int touts; /* #timeouts */
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int perrs; /* #parity errors */
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int senses; /* #request sense commands sent */
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ushort lubusy; /* What local units/subr. are busy? */
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u_char flags;
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#define T_NEED_TO_RESET 0x01 /* Should send a BUS_DEV_RESET */
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#define T_NEGOTIATE 0x02 /* (Re)Negotiate synchronous options */
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#define T_BUSY 0x04 /* Target is busy, i.e. cmd in progress */
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#define T_SYNCMODE 0x08 /* sync mode has been negotiated */
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#define T_SYNCHOFF 0x10 /* .. */
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#define T_RSELECTOFF 0x20 /* .. */
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u_char period; /* Period suggestion */
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u_char offset; /* Offset suggestion */
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} tinfo_t;
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/* Register a linenumber (for debugging) */
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#define LOGLINE(p)
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#define ESP_SHOWECBS 0x01
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#define ESP_SHOWINTS 0x02
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#define ESP_SHOWCMDS 0x04
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#define ESP_SHOWMISC 0x08
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#define ESP_SHOWTRAC 0x10
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#define ESP_SHOWSTART 0x20
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#define ESP_SHOWPHASE 0x40
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#define ESP_SHOWDMA 0x80
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#define ESP_SHOWCCMDS 0x100
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#define ESP_SHOWMSGS 0x200
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#ifdef ESP_DEBUG
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extern int esp_debug;
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#define ESP_ECBS(str) do {if (esp_debug & ESP_SHOWECBS) printf str;} while (0)
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#define ESP_MISC(str) do {if (esp_debug & ESP_SHOWMISC) printf str;} while (0)
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#define ESP_INTS(str) do {if (esp_debug & ESP_SHOWINTS) printf str;} while (0)
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#define ESP_TRACE(str) do {if (esp_debug & ESP_SHOWTRAC) printf str;} while (0)
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#define ESP_CMDS(str) do {if (esp_debug & ESP_SHOWCMDS) printf str;} while (0)
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#define ESP_START(str) do {if (esp_debug & ESP_SHOWSTART) printf str;}while (0)
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#define ESP_PHASE(str) do {if (esp_debug & ESP_SHOWPHASE) printf str;}while (0)
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#define ESP_DMA(str) do {if (esp_debug & ESP_SHOWDMA) printf str;}while (0)
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#define ESP_MSGS(str) do {if (esp_debug & ESP_SHOWMSGS) printf str;}while (0)
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#else
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#define ESP_ECBS(str)
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#define ESP_MISC(str)
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#define ESP_INTS(str)
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#define ESP_TRACE(str)
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#define ESP_CMDS(str)
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#define ESP_START(str)
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#define ESP_PHASE(str)
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#define ESP_DMA(str)
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#define ESP_MSGS(str)
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#endif
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#define ESP_MAX_MSG_LEN 8
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struct esp_softc {
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struct device sc_dev; /* us as a device */
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#ifdef SPARC_DRIVER
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struct sbusdev sc_sd; /* sbus device */
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struct intrhand sc_ih; /* intr handler */
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#endif
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struct evcnt sc_intrcnt; /* intr count */
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struct scsi_link sc_link; /* scsi lint struct */
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#ifdef SPARC_DRIVER
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volatile u_char *sc_reg; /* the registers */
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struct dma_softc *sc_dma; /* pointer to my dma */
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#else
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#ifdef MAC68K_DRIVER
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volatile u_char *sc_reg; /* the registers */
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struct dma_softc _sc_dma; /* my (fake) DMA structure */
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struct dma_softc *sc_dma; /* pointer to my (fake) DMA */
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u_char irq_mask; /* mask for clearing IRQ */
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#else
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volatile u_int32_t *sc_reg; /* the registers */
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struct tcds_slotconfig *sc_dma; /* DMA/slot info lives here. */
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void *sc_cookie; /* intr. handling cookie */
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#endif
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#endif
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/* register defaults */
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u_char sc_cfg1; /* Config 1 */
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u_char sc_cfg2; /* Config 2, not ESP100 */
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u_char sc_cfg3; /* Config 3, only ESP200 */
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u_char sc_ccf; /* Clock Conversion */
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u_char sc_timeout;
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/* register copies, see espreadregs() */
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u_char sc_espintr;
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u_char sc_espstat;
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u_char sc_espstep;
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u_char sc_espfflags;
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/* Lists of command blocks */
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TAILQ_HEAD(ecb_list, esp_ecb) free_list,
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ready_list,
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nexus_list;
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struct esp_ecb *sc_nexus; /* current command */
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struct esp_ecb sc_ecb[8]; /* one per target */
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struct esp_tinfo sc_tinfo[8];
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/* Data about the current nexus (updated for every cmd switch) */
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caddr_t sc_dp; /* Current data pointer */
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ssize_t sc_dleft; /* Data left to transfer */
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/* Adapter state */
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int sc_phase; /* Copy of what bus phase we are in */
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int sc_prevphase; /* Copy of what bus phase we were in */
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u_char sc_state; /* State applicable to the adapter */
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u_char sc_flags;
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u_char sc_selid;
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u_char sc_lastcmd;
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/* Message stuff */
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u_char sc_msgpriq; /* One or more messages to send (encoded) */
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u_char sc_msgout; /* What message is on its way out? */
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u_char sc_msgoutq; /* What messages have been sent so far? */
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u_char sc_omess[ESP_MAX_MSG_LEN];
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caddr_t sc_omp; /* Message pointer (for multibyte messages) */
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size_t sc_omlen;
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u_char sc_imess[ESP_MAX_MSG_LEN + 1];
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caddr_t sc_imp; /* Message pointer (for multibyte messages) */
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size_t sc_imlen;
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/* hardware/openprom stuff */
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int sc_node; /* PROM node ID */
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int sc_freq; /* Freq in HZ */
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#ifdef SPARC_DRIVER
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int sc_pri; /* SBUS priority */
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#endif
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int sc_id; /* our scsi id */
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int sc_rev; /* esp revision */
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int sc_minsync; /* minimum sync period / 4 */
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int sc_maxxfer; /* maximum transfer size */
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};
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/* values for sc_state */
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#define ESP_IDLE 1 /* waiting for something to do */
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#define ESP_SELECTING 2 /* SCSI command is arbiting */
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#define ESP_RESELECTED 3 /* Has been reselected */
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#define ESP_CONNECTED 4 /* Actively using the SCSI bus */
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#define ESP_DISCONNECT 5 /* MSG_DISCONNECT received */
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#define ESP_CMDCOMPLETE 6 /* MSG_CMDCOMPLETE received */
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#define ESP_CLEANING 7
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#define ESP_SBR 8 /* Expect a SCSI RST because we commanded it */
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/* values for sc_flags */
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#define ESP_DROP_MSGI 0x01 /* Discard all msgs (parity err detected) */
|
||||
#define ESP_ABORTING 0x02 /* Bailing out */
|
||||
#define ESP_DOINGDMA 0x04 /* The FIFO data path is active! */
|
||||
#define ESP_SYNCHNEGO 0x08 /* Synch negotiation in progress. */
|
||||
#define ESP_ICCS 0x10 /* Expect status phase results */
|
||||
#define ESP_WAITI 0x20 /* Waiting for non-DMA data to arrive */
|
||||
#define ESP_ATN 0x40 /* ATN asserted */
|
||||
|
||||
/* values for sc_msgout */
|
||||
#define SEND_DEV_RESET 0x01
|
||||
#define SEND_PARITY_ERROR 0x02
|
||||
#define SEND_INIT_DET_ERR 0x04
|
||||
#define SEND_REJECT 0x08
|
||||
#define SEND_IDENTIFY 0x10
|
||||
#define SEND_ABORT 0x20
|
||||
#define SEND_SDTR 0x40
|
||||
#define SEND_WDTR 0x80
|
||||
|
||||
/* SCSI Status codes */
|
||||
#define ST_MASK 0x3e /* bit 0,6,7 is reserved */
|
||||
|
||||
/* phase bits */
|
||||
#define IOI 0x01
|
||||
#define CDI 0x02
|
||||
#define MSGI 0x04
|
||||
|
||||
/* Information transfer phases */
|
||||
#define DATA_OUT_PHASE (0)
|
||||
#define DATA_IN_PHASE (IOI)
|
||||
#define COMMAND_PHASE (CDI)
|
||||
#define STATUS_PHASE (CDI|IOI)
|
||||
#define MESSAGE_OUT_PHASE (MSGI|CDI)
|
||||
#define MESSAGE_IN_PHASE (MSGI|CDI|IOI)
|
||||
|
||||
#define PHASE_MASK (MSGI|CDI|IOI)
|
||||
|
||||
/* Some pseudo phases for getphase()*/
|
||||
#define BUSFREE_PHASE 0x100 /* Re/Selection no longer valid */
|
||||
#define INVALID_PHASE 0x101 /* Re/Selection valid, but no REQ yet */
|
||||
#define PSEUDO_PHASE 0x100 /* "pseudo" bit */
|
||||
|
||||
/*
|
||||
* Macros to read and write the chip's registers.
|
||||
*/
|
||||
#ifdef SPARC_DRIVER
|
||||
#define ESP_READ_REG(sc, reg) \
|
||||
((sc)->sc_reg[(reg) * 4])
|
||||
#define ESP_WRITE_REG(sc, reg, val) \
|
||||
do { \
|
||||
u_char v = (val); \
|
||||
(sc)->sc_reg[(reg) * 4] = v; \
|
||||
} while (0)
|
||||
#else /* ! SPARC_DRIVER */
|
||||
#ifdef MAC68K_DRIVER
|
||||
#define ESP_READ_REG(sc, reg) \
|
||||
((sc)->sc_reg[(reg) * 16])
|
||||
#define ESP_WRITE_REG(sc, reg, val) \
|
||||
do { \
|
||||
u_char v = (val); \
|
||||
(sc)->sc_reg[(reg) * 16] = v; \
|
||||
} while (0)
|
||||
#else
|
||||
#if 1
|
||||
static inline u_char
|
||||
ESP_READ_REG(sc, reg)
|
||||
struct esp_softc *sc;
|
||||
int reg;
|
||||
{
|
||||
u_char v;
|
||||
|
||||
v = sc->sc_reg[reg * 2] & 0xff;
|
||||
alpha_mb();
|
||||
return v;
|
||||
}
|
||||
#else
|
||||
#define ESP_READ_REG(sc, reg) \
|
||||
((u_char)((sc)->sc_reg[(reg) * 2] & 0xff))
|
||||
#endif
|
||||
#define ESP_WRITE_REG(sc, reg, val) \
|
||||
do { \
|
||||
u_char v = (val); \
|
||||
(sc)->sc_reg[(reg) * 2] = v; \
|
||||
alpha_mb(); \
|
||||
} while (0)
|
||||
#endif /* MAC68K_DRIVER */
|
||||
#endif /* SPARC_DRIVER */
|
||||
|
||||
#ifdef ESP_DEBUG
|
||||
#define ESPCMD(sc, cmd) do { \
|
||||
if (esp_debug & ESP_SHOWCCMDS) \
|
||||
printf("<cmd:0x%x>", (unsigned)cmd); \
|
||||
sc->sc_lastcmd = cmd; \
|
||||
ESP_WRITE_REG(sc, ESP_CMD, cmd); \
|
||||
} while (0)
|
||||
#else
|
||||
#define ESPCMD(sc, cmd) ESP_WRITE_REG(sc, ESP_CMD, cmd)
|
||||
#endif
|
||||
|
||||
#define SAME_ESP(sc, bp, ca) \
|
||||
((bp->val[0] == ca->ca_slot && bp->val[1] == ca->ca_offset) || \
|
||||
(bp->val[0] == -1 && bp->val[1] == sc->sc_dev.dv_unit))
|
||||
|
||||
#ifndef SPARC_DRIVER
|
||||
|
||||
#ifdef MAC68K_DRIVER
|
||||
|
||||
/* DMA macros for ESP */
|
||||
#define DMA_ISINTR(sc) (ESP_READ_REG((sc)->sc_esp, ESP_STAT) & 0x80)
|
||||
#define DMA_RESET(sc) do { (sc)->sc_active = 0; } while(0)
|
||||
#define DMA_INTR(sc) dma_intr(sc)
|
||||
#define DMA_SETUP(sc, paddr, plen, datain, pdmasize) \
|
||||
do { \
|
||||
(sc)->sc_dmaaddr = paddr; \
|
||||
(sc)->sc_pdmalen = plen; \
|
||||
(sc)->sc_datain = datain; \
|
||||
(sc)->sc_dmasize = *pdmasize; \
|
||||
} while (0)
|
||||
|
||||
#define DMA_GO(sc) \
|
||||
do { \
|
||||
if ((sc)->sc_datain == 0) { \
|
||||
ESP_WRITE_REG((sc)->sc_esp, \
|
||||
ESP_FIFO, **(sc)->sc_dmaaddr); \
|
||||
(*(sc)->sc_pdmalen)--; \
|
||||
} \
|
||||
(sc)->sc_active = 1; \
|
||||
} while (0)
|
||||
|
||||
#define DMA_ISACTIVE(sc) ((sc)->sc_active)
|
||||
|
||||
#else MAC68K_DRIVER
|
||||
|
||||
/* DMA macros for ESP */
|
||||
#define DMA_ISINTR(sc) tcds_dma_isintr(sc)
|
||||
#define DMA_RESET(sc) tcds_dma_reset(sc)
|
||||
#define DMA_INTR(sc) tcds_dma_intr(sc)
|
||||
#define DMA_SETUP(sc, addr, len, datain, dmasize) \
|
||||
tcds_dma_setup(sc, addr, len, datain, dmasize)
|
||||
#define DMA_GO(sc) tcds_dma_go(sc)
|
||||
#define DMA_ISACTIVE(sc) tcds_dma_isactive(sc)
|
||||
|
||||
#endif /* MAC68K_DRIVER */
|
||||
#endif /* SPARC_DRIVER */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,391 @@
|
|||
/* $NetBSD: espvar.h,v 1.1 1996/10/29 06:09:00 briggs Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1994 Peter Galbavy. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Peter Galbavy.
|
||||
* 4. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <machine/param.h>
|
||||
|
||||
#if defined(__sparc__) && !defined(SPARC_DRIVER)
|
||||
#define SPARC_DRIVER
|
||||
#else
|
||||
#if (_MACHINE == mac68k) && !defined(MAC68K_DRIVER)
|
||||
#define MAC68K_DRIVER
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define ESP_DEBUG 0
|
||||
|
||||
#define ESP_ABORT_TIMEOUT 2000 /* time to wait for abort */
|
||||
|
||||
#define FREQTOCCF(freq) (((freq + 4) / 5))
|
||||
|
||||
/* esp revisions */
|
||||
#define ESP100 0x01
|
||||
#define ESP100A 0x02
|
||||
#define ESP200 0x03
|
||||
#define NCR53C94 0x04
|
||||
#define NCR53C96 0x05
|
||||
|
||||
/*
|
||||
* ECB. Holds additional information for each SCSI command Comments: We
|
||||
* need a separate scsi command block because we may need to overwrite it
|
||||
* with a request sense command. Basicly, we refrain from fiddling with
|
||||
* the scsi_xfer struct (except do the expected updating of return values).
|
||||
* We'll generally update: xs->{flags,resid,error,sense,status} and
|
||||
* occasionally xs->retries.
|
||||
*/
|
||||
struct esp_ecb {
|
||||
TAILQ_ENTRY(esp_ecb) chain;
|
||||
struct scsi_xfer *xs; /* SCSI xfer ctrl block from above */
|
||||
int flags;
|
||||
#define ECB_ALLOC 0x01
|
||||
#define ECB_NEXUS 0x02
|
||||
#define ECB_SENSE 0x04
|
||||
#define ECB_ABORT 0x40
|
||||
#define ECB_RESET 0x80
|
||||
int timeout;
|
||||
|
||||
struct scsi_generic cmd; /* SCSI command block */
|
||||
int clen;
|
||||
char *daddr; /* Saved data pointer */
|
||||
int dleft; /* Residue */
|
||||
u_char stat; /* SCSI status byte */
|
||||
|
||||
#if ESP_DEBUG > 0
|
||||
char trace[1000];
|
||||
#endif
|
||||
};
|
||||
#if ESP_DEBUG > 0
|
||||
#define ECB_TRACE(ecb, msg, a, b) do { \
|
||||
const char *f = "[" msg "]"; \
|
||||
int n = strlen((ecb)->trace); \
|
||||
if (n < (sizeof((ecb)->trace)-100)) \
|
||||
sprintf((ecb)->trace + n, f, a, b); \
|
||||
} while(0)
|
||||
#else
|
||||
#define ECB_TRACE(ecb, msg, a, b)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Some info about each (possible) target on the SCSI bus. This should
|
||||
* probably have been a "per target+lunit" structure, but we'll leave it at
|
||||
* this for now. Is there a way to reliably hook it up to sc->fordriver??
|
||||
*/
|
||||
struct esp_tinfo {
|
||||
int cmds; /* #commands processed */
|
||||
int dconns; /* #disconnects */
|
||||
int touts; /* #timeouts */
|
||||
int perrs; /* #parity errors */
|
||||
int senses; /* #request sense commands sent */
|
||||
ushort lubusy; /* What local units/subr. are busy? */
|
||||
u_char flags;
|
||||
#define T_NEED_TO_RESET 0x01 /* Should send a BUS_DEV_RESET */
|
||||
#define T_NEGOTIATE 0x02 /* (Re)Negotiate synchronous options */
|
||||
#define T_BUSY 0x04 /* Target is busy, i.e. cmd in progress */
|
||||
#define T_SYNCMODE 0x08 /* sync mode has been negotiated */
|
||||
#define T_SYNCHOFF 0x10 /* .. */
|
||||
#define T_RSELECTOFF 0x20 /* .. */
|
||||
u_char period; /* Period suggestion */
|
||||
u_char offset; /* Offset suggestion */
|
||||
} tinfo_t;
|
||||
|
||||
/* Register a linenumber (for debugging) */
|
||||
#define LOGLINE(p)
|
||||
|
||||
#define ESP_SHOWECBS 0x01
|
||||
#define ESP_SHOWINTS 0x02
|
||||
#define ESP_SHOWCMDS 0x04
|
||||
#define ESP_SHOWMISC 0x08
|
||||
#define ESP_SHOWTRAC 0x10
|
||||
#define ESP_SHOWSTART 0x20
|
||||
#define ESP_SHOWPHASE 0x40
|
||||
#define ESP_SHOWDMA 0x80
|
||||
#define ESP_SHOWCCMDS 0x100
|
||||
#define ESP_SHOWMSGS 0x200
|
||||
|
||||
#ifdef ESP_DEBUG
|
||||
extern int esp_debug;
|
||||
#define ESP_ECBS(str) do {if (esp_debug & ESP_SHOWECBS) printf str;} while (0)
|
||||
#define ESP_MISC(str) do {if (esp_debug & ESP_SHOWMISC) printf str;} while (0)
|
||||
#define ESP_INTS(str) do {if (esp_debug & ESP_SHOWINTS) printf str;} while (0)
|
||||
#define ESP_TRACE(str) do {if (esp_debug & ESP_SHOWTRAC) printf str;} while (0)
|
||||
#define ESP_CMDS(str) do {if (esp_debug & ESP_SHOWCMDS) printf str;} while (0)
|
||||
#define ESP_START(str) do {if (esp_debug & ESP_SHOWSTART) printf str;}while (0)
|
||||
#define ESP_PHASE(str) do {if (esp_debug & ESP_SHOWPHASE) printf str;}while (0)
|
||||
#define ESP_DMA(str) do {if (esp_debug & ESP_SHOWDMA) printf str;}while (0)
|
||||
#define ESP_MSGS(str) do {if (esp_debug & ESP_SHOWMSGS) printf str;}while (0)
|
||||
#else
|
||||
#define ESP_ECBS(str)
|
||||
#define ESP_MISC(str)
|
||||
#define ESP_INTS(str)
|
||||
#define ESP_TRACE(str)
|
||||
#define ESP_CMDS(str)
|
||||
#define ESP_START(str)
|
||||
#define ESP_PHASE(str)
|
||||
#define ESP_DMA(str)
|
||||
#define ESP_MSGS(str)
|
||||
#endif
|
||||
|
||||
#define ESP_MAX_MSG_LEN 8
|
||||
|
||||
struct esp_softc {
|
||||
struct device sc_dev; /* us as a device */
|
||||
#ifdef SPARC_DRIVER
|
||||
struct sbusdev sc_sd; /* sbus device */
|
||||
struct intrhand sc_ih; /* intr handler */
|
||||
#endif
|
||||
struct evcnt sc_intrcnt; /* intr count */
|
||||
struct scsi_link sc_link; /* scsi lint struct */
|
||||
#ifdef SPARC_DRIVER
|
||||
volatile u_char *sc_reg; /* the registers */
|
||||
struct dma_softc *sc_dma; /* pointer to my dma */
|
||||
#else
|
||||
#ifdef MAC68K_DRIVER
|
||||
volatile u_char *sc_reg; /* the registers */
|
||||
struct dma_softc _sc_dma; /* my (fake) DMA structure */
|
||||
struct dma_softc *sc_dma; /* pointer to my (fake) DMA */
|
||||
u_char irq_mask; /* mask for clearing IRQ */
|
||||
#else
|
||||
volatile u_int32_t *sc_reg; /* the registers */
|
||||
struct tcds_slotconfig *sc_dma; /* DMA/slot info lives here. */
|
||||
void *sc_cookie; /* intr. handling cookie */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* register defaults */
|
||||
u_char sc_cfg1; /* Config 1 */
|
||||
u_char sc_cfg2; /* Config 2, not ESP100 */
|
||||
u_char sc_cfg3; /* Config 3, only ESP200 */
|
||||
u_char sc_ccf; /* Clock Conversion */
|
||||
u_char sc_timeout;
|
||||
|
||||
/* register copies, see espreadregs() */
|
||||
u_char sc_espintr;
|
||||
u_char sc_espstat;
|
||||
u_char sc_espstep;
|
||||
u_char sc_espfflags;
|
||||
|
||||
/* Lists of command blocks */
|
||||
TAILQ_HEAD(ecb_list, esp_ecb) free_list,
|
||||
ready_list,
|
||||
nexus_list;
|
||||
|
||||
struct esp_ecb *sc_nexus; /* current command */
|
||||
struct esp_ecb sc_ecb[8]; /* one per target */
|
||||
struct esp_tinfo sc_tinfo[8];
|
||||
|
||||
/* Data about the current nexus (updated for every cmd switch) */
|
||||
caddr_t sc_dp; /* Current data pointer */
|
||||
ssize_t sc_dleft; /* Data left to transfer */
|
||||
|
||||
/* Adapter state */
|
||||
int sc_phase; /* Copy of what bus phase we are in */
|
||||
int sc_prevphase; /* Copy of what bus phase we were in */
|
||||
u_char sc_state; /* State applicable to the adapter */
|
||||
u_char sc_flags;
|
||||
u_char sc_selid;
|
||||
u_char sc_lastcmd;
|
||||
|
||||
/* Message stuff */
|
||||
u_char sc_msgpriq; /* One or more messages to send (encoded) */
|
||||
u_char sc_msgout; /* What message is on its way out? */
|
||||
u_char sc_msgoutq; /* What messages have been sent so far? */
|
||||
u_char sc_omess[ESP_MAX_MSG_LEN];
|
||||
caddr_t sc_omp; /* Message pointer (for multibyte messages) */
|
||||
size_t sc_omlen;
|
||||
u_char sc_imess[ESP_MAX_MSG_LEN + 1];
|
||||
caddr_t sc_imp; /* Message pointer (for multibyte messages) */
|
||||
size_t sc_imlen;
|
||||
|
||||
/* hardware/openprom stuff */
|
||||
int sc_node; /* PROM node ID */
|
||||
int sc_freq; /* Freq in HZ */
|
||||
#ifdef SPARC_DRIVER
|
||||
int sc_pri; /* SBUS priority */
|
||||
#endif
|
||||
int sc_id; /* our scsi id */
|
||||
int sc_rev; /* esp revision */
|
||||
int sc_minsync; /* minimum sync period / 4 */
|
||||
int sc_maxxfer; /* maximum transfer size */
|
||||
};
|
||||
|
||||
/* values for sc_state */
|
||||
#define ESP_IDLE 1 /* waiting for something to do */
|
||||
#define ESP_SELECTING 2 /* SCSI command is arbiting */
|
||||
#define ESP_RESELECTED 3 /* Has been reselected */
|
||||
#define ESP_CONNECTED 4 /* Actively using the SCSI bus */
|
||||
#define ESP_DISCONNECT 5 /* MSG_DISCONNECT received */
|
||||
#define ESP_CMDCOMPLETE 6 /* MSG_CMDCOMPLETE received */
|
||||
#define ESP_CLEANING 7
|
||||
#define ESP_SBR 8 /* Expect a SCSI RST because we commanded it */
|
||||
|
||||
/* values for sc_flags */
|
||||
#define ESP_DROP_MSGI 0x01 /* Discard all msgs (parity err detected) */
|
||||
#define ESP_ABORTING 0x02 /* Bailing out */
|
||||
#define ESP_DOINGDMA 0x04 /* The FIFO data path is active! */
|
||||
#define ESP_SYNCHNEGO 0x08 /* Synch negotiation in progress. */
|
||||
#define ESP_ICCS 0x10 /* Expect status phase results */
|
||||
#define ESP_WAITI 0x20 /* Waiting for non-DMA data to arrive */
|
||||
#define ESP_ATN 0x40 /* ATN asserted */
|
||||
|
||||
/* values for sc_msgout */
|
||||
#define SEND_DEV_RESET 0x01
|
||||
#define SEND_PARITY_ERROR 0x02
|
||||
#define SEND_INIT_DET_ERR 0x04
|
||||
#define SEND_REJECT 0x08
|
||||
#define SEND_IDENTIFY 0x10
|
||||
#define SEND_ABORT 0x20
|
||||
#define SEND_SDTR 0x40
|
||||
#define SEND_WDTR 0x80
|
||||
|
||||
/* SCSI Status codes */
|
||||
#define ST_MASK 0x3e /* bit 0,6,7 is reserved */
|
||||
|
||||
/* phase bits */
|
||||
#define IOI 0x01
|
||||
#define CDI 0x02
|
||||
#define MSGI 0x04
|
||||
|
||||
/* Information transfer phases */
|
||||
#define DATA_OUT_PHASE (0)
|
||||
#define DATA_IN_PHASE (IOI)
|
||||
#define COMMAND_PHASE (CDI)
|
||||
#define STATUS_PHASE (CDI|IOI)
|
||||
#define MESSAGE_OUT_PHASE (MSGI|CDI)
|
||||
#define MESSAGE_IN_PHASE (MSGI|CDI|IOI)
|
||||
|
||||
#define PHASE_MASK (MSGI|CDI|IOI)
|
||||
|
||||
/* Some pseudo phases for getphase()*/
|
||||
#define BUSFREE_PHASE 0x100 /* Re/Selection no longer valid */
|
||||
#define INVALID_PHASE 0x101 /* Re/Selection valid, but no REQ yet */
|
||||
#define PSEUDO_PHASE 0x100 /* "pseudo" bit */
|
||||
|
||||
/*
|
||||
* Macros to read and write the chip's registers.
|
||||
*/
|
||||
#ifdef SPARC_DRIVER
|
||||
#define ESP_READ_REG(sc, reg) \
|
||||
((sc)->sc_reg[(reg) * 4])
|
||||
#define ESP_WRITE_REG(sc, reg, val) \
|
||||
do { \
|
||||
u_char v = (val); \
|
||||
(sc)->sc_reg[(reg) * 4] = v; \
|
||||
} while (0)
|
||||
#else /* ! SPARC_DRIVER */
|
||||
#ifdef MAC68K_DRIVER
|
||||
#define ESP_READ_REG(sc, reg) \
|
||||
((sc)->sc_reg[(reg) * 16])
|
||||
#define ESP_WRITE_REG(sc, reg, val) \
|
||||
do { \
|
||||
u_char v = (val); \
|
||||
(sc)->sc_reg[(reg) * 16] = v; \
|
||||
} while (0)
|
||||
#else
|
||||
#if 1
|
||||
static inline u_char
|
||||
ESP_READ_REG(sc, reg)
|
||||
struct esp_softc *sc;
|
||||
int reg;
|
||||
{
|
||||
u_char v;
|
||||
|
||||
v = sc->sc_reg[reg * 2] & 0xff;
|
||||
alpha_mb();
|
||||
return v;
|
||||
}
|
||||
#else
|
||||
#define ESP_READ_REG(sc, reg) \
|
||||
((u_char)((sc)->sc_reg[(reg) * 2] & 0xff))
|
||||
#endif
|
||||
#define ESP_WRITE_REG(sc, reg, val) \
|
||||
do { \
|
||||
u_char v = (val); \
|
||||
(sc)->sc_reg[(reg) * 2] = v; \
|
||||
alpha_mb(); \
|
||||
} while (0)
|
||||
#endif /* MAC68K_DRIVER */
|
||||
#endif /* SPARC_DRIVER */
|
||||
|
||||
#ifdef ESP_DEBUG
|
||||
#define ESPCMD(sc, cmd) do { \
|
||||
if (esp_debug & ESP_SHOWCCMDS) \
|
||||
printf("<cmd:0x%x>", (unsigned)cmd); \
|
||||
sc->sc_lastcmd = cmd; \
|
||||
ESP_WRITE_REG(sc, ESP_CMD, cmd); \
|
||||
} while (0)
|
||||
#else
|
||||
#define ESPCMD(sc, cmd) ESP_WRITE_REG(sc, ESP_CMD, cmd)
|
||||
#endif
|
||||
|
||||
#define SAME_ESP(sc, bp, ca) \
|
||||
((bp->val[0] == ca->ca_slot && bp->val[1] == ca->ca_offset) || \
|
||||
(bp->val[0] == -1 && bp->val[1] == sc->sc_dev.dv_unit))
|
||||
|
||||
#ifndef SPARC_DRIVER
|
||||
|
||||
#ifdef MAC68K_DRIVER
|
||||
|
||||
/* DMA macros for ESP */
|
||||
#define DMA_ISINTR(sc) (ESP_READ_REG((sc)->sc_esp, ESP_STAT) & 0x80)
|
||||
#define DMA_RESET(sc) do { (sc)->sc_active = 0; } while(0)
|
||||
#define DMA_INTR(sc) dma_intr(sc)
|
||||
#define DMA_SETUP(sc, paddr, plen, datain, pdmasize) \
|
||||
do { \
|
||||
(sc)->sc_dmaaddr = paddr; \
|
||||
(sc)->sc_pdmalen = plen; \
|
||||
(sc)->sc_datain = datain; \
|
||||
(sc)->sc_dmasize = *pdmasize; \
|
||||
} while (0)
|
||||
|
||||
#define DMA_GO(sc) \
|
||||
do { \
|
||||
if ((sc)->sc_datain == 0) { \
|
||||
ESP_WRITE_REG((sc)->sc_esp, \
|
||||
ESP_FIFO, **(sc)->sc_dmaaddr); \
|
||||
(*(sc)->sc_pdmalen)--; \
|
||||
} \
|
||||
(sc)->sc_active = 1; \
|
||||
} while (0)
|
||||
|
||||
#define DMA_ISACTIVE(sc) ((sc)->sc_active)
|
||||
|
||||
#else MAC68K_DRIVER
|
||||
|
||||
/* DMA macros for ESP */
|
||||
#define DMA_ISINTR(sc) tcds_dma_isintr(sc)
|
||||
#define DMA_RESET(sc) tcds_dma_reset(sc)
|
||||
#define DMA_INTR(sc) tcds_dma_intr(sc)
|
||||
#define DMA_SETUP(sc, addr, len, datain, dmasize) \
|
||||
tcds_dma_setup(sc, addr, len, datain, dmasize)
|
||||
#define DMA_GO(sc) tcds_dma_go(sc)
|
||||
#define DMA_ISACTIVE(sc) tcds_dma_isactive(sc)
|
||||
|
||||
#endif /* MAC68K_DRIVER */
|
||||
#endif /* SPARC_DRIVER */
|
||||
Loading…
Reference in New Issue