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Fix timer initialization so that we don't gain one extra microsecond per 

second on Sun4m machines. Although this was in the noise of the unstable
Sun clock crystals before, the discrepancy amounted to about 100 ppm, and
thus made NTP perform poorly. NTP now works happily on my SS20...
This commit is contained in:
abrown 1996-10-28 00:20:31 +00:00
parent f5927ca260
commit cafb62af25
2 changed files with 17 additions and 13 deletions
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8
sys/arch/sparc/sparc/clock.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: clock.c,v 1.47 1996/10/13 03:00:29 christos Exp $ */
/* $NetBSD: clock.c,v 1.48 1996/10/28 00:20:31 abrown Exp $ */
/*
* Copyright (c) 1992, 1993
@ -640,8 +640,8 @@ cpu_initclocks()
statvar >>= 1;
if (CPU_ISSUN4M) {
timerreg_4m->t_limit = tmr_ustolim(tick);
counterreg_4m->t_limit = tmr_ustolim(statint);
timerreg_4m->t_limit = tmr_ustolim4m(tick);
counterreg_4m->t_limit = tmr_ustolim4m(statint);
}
if (CPU_ISSUN4OR4C) {
@ -767,7 +767,7 @@ statintr(cap)
newint = statmin + r;
if (CPU_ISSUN4M) {
counterreg_4m->t_limit = tmr_ustolim(newint);
counterreg_4m->t_limit = tmr_ustolim4m(newint);
}
if (CPU_ISSUN4OR4C) {

22
sys/arch/sparc/sparc/timerreg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: timerreg.h,v 1.5 1996/05/02 18:17:33 pk Exp $ */
/* $NetBSD: timerreg.h,v 1.6 1996/10/28 00:20:32 abrown Exp $ */
/*
* Copyright (c) 1992, 1993
@ -74,12 +74,6 @@
* they count in 500ns increments (bit 9 being the least
* significant bit).
*
* Note that we still use the `sun4c' masks and shifts to compute
* the bit pattern, given the tick period in microseconds, resulting
* in a limit value that is 1 too high. This means that (with HZ=100)
* the clock will err on the slow side by 500ns/10ms (or 0.00005 %).
* We dont bother.
*
*/
#ifndef _LOCORE
struct timer_4 {
@ -118,8 +112,18 @@ struct counter_4m { /* counter that interrupts at ipl 14 */
#define TMR_SHIFT 10 /* shift to obtain microseconds */
#define TMR_MASK 0x1fffff /* 21 bits */
/* Compute a limit that causes the timer to fire every n microseconds. */
/*
* Compute a limit that causes the timer to fire every n microseconds.
* The Sun4c requires that the timer register be initialized for n+1
* microseconds, while the Sun4m requires it be initialized for n. Thus
* the two versions of this function.
*
* Note that the manual for the chipset used in the Sun4m suggests that
* the timer be set at n+0.5 microseconds; in practice, this produces
* a 50 ppm clock skew, which means that the 0.5 should not be there...
*/
#define tmr_ustolim(n) (((n) + 1) << TMR_SHIFT)
/*efine TMR_SHIFT4M 9 -* shift to obtain microseconds */
/*efine tmr_ustolim(n) (((2*(n)) + 1) << TMR_SHIFT4M)*/
/*efine tmr_ustolim4m(n) (((2*(n)) + 1) << TMR_SHIFT4M)*/
#define tmr_ustolim4m(n) ((n) << TMR_SHIFT)