came from kernel mode. Otherwise, print details of the exception
and send a SIGILL to the process.
The is necessary now that debug exceptions are handled here.
possible to use alternate system call tables. This is usefull for
displaying correctly the arguments in Mach binaries traces.
If NULL is given, then the regular systam call table for the process is used.
under some circumstances, leave turds in the icache following vmspace
teardown.
It's not yet clear if this is a pmap bug or a toolchain problem since
the hack is unecessary when the kernel is compiled with -O0. Of course
that could just be masking the problem due to increased icache pressure...
- Overhaul the TLB management code such that we now keep track of
the exact TLB slot at which a mapping was inserted, both for user-
space and kernel mappings. This addresses #2 on the TODO list.
original system call number, which can be negative for a Mach trap.
We cannot just replace code by realcode, because ktrsyscall uses it as
an index in the system call table, thus crashing the kernel when the
value is negative.
unmanaged mappings) so we can deal with cache aliases, make sure to
skip unmanaged/wired mappings (added via pmap_kenter_pa()) when doing
things like pmap_page_protect().
kqueue provides a stateful and efficient event notification framework
currently supported events include socket, file, directory, fifo,
pipe, tty and device changes, and monitoring of processes and signals
kqueue is supported by all writable filesystems in NetBSD tree
(with exception of Coda) and all device drivers supporting poll(2)
based on work done by Jonathan Lemon for FreeBSD
initial NetBSD port done by Luke Mewburn and Jason Thorpe
- Shift a leading misaligned quad to compensate for the implicit shift
in the "ldlo.q" instruction. (And remove the "XXX:" comment which correctly
hinted that this might be necessary).
- Clean up some comments.
alignment code. (There was nothing wrong with the original code path
other than it was slightly slower if the buffer was already aligned).
Also, catch another corner case related to alignment/length of the
last 1-7 bytes.
using a "movi imm, Rn / sub R15, RN, R15" pair. This is how the compiler
creates frames which are too big to fit in the immediate field of "addi";
something which happens a lot with -O0 ...
While I'm here, add a simple heuristic to detect infinite loops caused by
tracing back through some non-leaf asm routines which don't set up frames.
- Allocate interrupt handles dynamically from a pool(9) to reduce the
number of TLB misses during interrupt dispatch.
- Fully support evcnt(9) in all interrupt dispatchers.
- Use the PVO_CACHEABLE flag in the pvo as the One True Indicator of
the cacheable status of a mapping instead of peeking at the PTEH.
- Don't inline some of the larger routines, in an effort to appease
the somewhat buggy compiler.
- Fix some comments.
- Fix some casts.
- Add a bunch more debugging instrumentation.
- Move usr, sr, pc, and the branch-target registers to the top of
the listing so that it is no longer necessary to scroll through
64 integer registers to see them.
The main bug fixes are:
- pmap_pvo_remove() must calculate the kipt index if the idx param is -1.
- Don't assume that if a pmap's ASID generation is out of date that we
can skip purging/invalidating the cache for any of its constituent
mappings. At this time, the ASID generation just indicates that none
of its mappings are in the TLB. However, there may still be some valid
cache entries for them.
Finally, the subtle NFS and buffer cache corruption problems disappear.
useful should one occur.
- Manually poke some config values into the sh5pci host bridge's
config registers since it doesn't appear in config. space.
- Reserve the first 256 bytes of i/o space to avoid assigning i/o
address 0 to any cards.
- Slight tweak to the initialisation code after consultation with
SuperH and the linux driver.
map accurately tracks the same flag in the segments belonging to it.
The map's copy can be set only if all the segments are coherent.
This finally gets NFS writes fully working on my PCI ex(4) card.
- Track unmanaged mappings of RAM more closely by allocating a pvo
for them. This allows us to check more accurately for multiple
cache-mode-incompatible mappings.
- As part of the above, implement pmap_steal_memory(). This has the
beneficial side-effect of moving a fair chunk of kernel data
structures into KSEG0.
pretty much working, at least for non-NFS use.
With NFS, it fails under pressure probably due to operand cache aliases
between KSEG0 and regular 4KB mappings elsewhere. Sigh.
operand cache synonyms and paradoxes for shared mappings:
- Writable mappings are cache-inhibited if the underlying physical
page is mapped at two or more *different* VAs.
This means that read-only mappings at different VAs are still
cacheable. While this could lead to operand cache synonyms, it
won't cause data loss. At worst, we'd have the same read-only
data in several cache-lines.
- If a new cache-inhibited mapping is added for a page which has
existing cacheable mappings, all the existing mappings must be
made cache-inhibited.
- Conversely, if a new cacheable mapping is added for a page which
has existing cache-inhibited mappings, the new mapping must also
be made cache-ibhibited.
- When a mapping is removed, see if we can upgrade any of the
underlying physical page's remaining mappings to cacheable.
TODO: Deal with operand cache aliases (if necessary).
of the loadable sections to correspond to the physical address of
RAM in the Cayman. This is so sh5gdb uploads the image to the correct
place. (Should've done this ages ago instead of manually running a
script...)
This can be removed when I get a native bootloader written.
cacheable attribute of a mapping.
- Honour PMAP_NC in pmap_enter() using NOCACHE, instead of DEVICE.
- No longer need to re-fetch the ptel in pmap_pa_unmap_kva() as
syncing the cache no longer risks causing a TLB miss.
- Re-define bus_size_t and bus_addr_t to be u_int32_t.
While this may well lose for future silicon with NEFFBITS > 32, the
original u_long was a waste on current designs (especially for _LP64).
Allocate/Prefetch one cache-line ahead of the one we're about to deal with.
This reduces the chances of the cpu stalling while waiting for the cache
to flush a dirty line in order to satisfy the Allocate/Prefetch request.
registers in any trap/interrupt exception frame found.
- Slight tweak to more accurately detect the correct call-site when
looking for a function's prologue.
This ensures we start from the actual call site, not the return address.
The latter may actually be in the next consecutive function if the current
function has the __noreturn__ attribute and the alignment is Just Right.
pointer, in case the caller grew its stack dynamically.
Also beef up the checks to catch cases where the call stack passes
through the exception handling code in locore. In this case, the
frame pointer and program counter are in the trapframe/intrframe.
problem, such that a TLB miss no longer occurs.
With the above, it is now safe to enable write-back caching for userland
mappings.
TODO: Deal with cache issues for shared mappings with different VAs.
- Add event counters for some key pmap events (similar to mpc6xx pmap).
- Use the cache-friendly, optimised copy/zero page functions.
- Add the necessary cache management code to enable WriteBack caching
of KSEG1 mappings. Seems to work fine so far.
- Use the PMAP_ASID_* constants from pmap.h
- Track pmap_pvo_{enter,remove}() depth in the same way as mpc6xx's pmap
(on which this pmap was originally based).
- Some misc. tidying up and added commentary.
- Use the VA/KVA to select whether to use the IPT or PTEG instead of
checking which pmap is being operated on.
- Add a handy DDB-callable function which will scan the kernel IPT
looking for inconsitencies.
- Finally, when unmapping a pool page, purge the data cache for the
page. This permits write-back caching to be enabled for kernel
text/data.
machine-specific code.
- Re-work the code which detects a nested critical section event.
We can now determine who is the owner of the critical section, and
what event occurred while it was owned.
- Work-around a silicon bug which can cause a nested critical event.
In the _EXCEPTION_ENTRY() macro (which sets up the critical section),
if there is a pending hardware interrupt which has a higher priority
than the current IMASK, then the "putcon" which supposedly clears SR.BL
and sets SR.IMASK to 0xf is not atomic. The pending hardware interrupt
will be taken, causing a nested critical section event. The work-around
is to update SR.BL and SR.IMASK separately using two "putcon" insns.
- Make it possible to at least *try* to resume execution if we
get an NMI.
- Major clean-up of the panic/critical section trap handlers.
The dumped state is now much more accurate.
scw