Commit Graph

971 Commits

Author SHA1 Message Date
castor a698752050 Disable FPU in sys___sigreturn14() so floating point registers are
properly restored.
2000-12-28 09:27:09 +00:00
castor a099ff1f75 Preserve the status register process_write_regs() to avoid confusion
about the current floating point context.
2000-12-27 08:28:12 +00:00
itojun efa2b7073c make mbstate_t bigger (32 -> 128 bytes).
XXX if you have libc after citrus locale import, please recompile libc,
and your applications that use mbstate_t (rather rare).  really sorry
for the mess.
2000-12-26 10:35:28 +00:00
nisimura 752dce24ae - fix typos in mips_user_cacheflush() and mips_user_cachectl().
- relocate those function declarations from include/pmap.h.
2000-12-25 08:56:12 +00:00
jdolecek e9e91a0fb5 split off thread specific stuff from struct sigacts to struct sigctx, leaving
only signal handler array sharable between threads
move other random signal stuff from struct proc to struct sigctx

This addresses kern/10981 by Matthew Orgass.
2000-12-22 22:58:52 +00:00
itojun 823498203f populate _BSD_MBSTATE_T_. add warning regarding to rune_t. 2000-12-21 06:03:47 +00:00
chs fc03073896 expose the tunables ubc_nwins and ubc_winsize in uvm_param.h.
add the space used by UBC mappings to the initial PTE calculations
for pmaps that do that (mips and alpha).
2000-12-21 00:52:01 +00:00
jeffs a68a400049 Hook mips3 cache error vector. No real handler, only set-up for a panic.
A real handler is hard.
2000-12-20 05:48:06 +00:00
jdolecek cacec11253 delete obsolete comment 2000-12-17 15:52:39 +00:00
jeffs 1c726aab7f For MIPS software masking option, when returning to user mode apply
the mask to all interrupts to catch changes in the mask state faster.
Does not affect platforms w/o this option enabled.
2000-12-14 21:29:51 +00:00
jeffs 19adf5c987 Make userret() "static __inline". This lets it be inlined, even if you
do not have the compiler inline normal functions to save space.  It helps
a bit on lmbench.
2000-12-14 21:24:53 +00:00
jdolecek ca57e681bd g/c obsolete vtrace(2) stuff 2000-12-13 18:13:05 +00:00
tsutsui c8a3a939e3 space -> TAB 2000-12-11 15:38:43 +00:00
tsutsui 7212823f47 Set USPACE_ALIGN to USPACE on mips. 2000-12-11 15:37:32 +00:00
chs b9423d9d52 in pmap_enter(), do not mark the page modified just because we mapped it
for write to a kernel address.  callers may now use the "flags" argument
to cause this to happen when desired.
2000-12-10 19:25:44 +00:00
matt 2e13ae83bc cpp/lorder/mkdep don't have cross specific versions. 2000-12-09 20:42:06 +00:00
matt cc1a776969 Add DEFGP/CROSSDIR for hpcmips. 2000-12-03 07:55:12 +00:00
matt b927e12eee Remove redundant depend of fp.S 2000-12-03 07:44:43 +00:00
matt 8bddbd2266 Include FP support if NOFPU is *NOT* defined. 2000-12-03 07:21:50 +00:00
matt 825cb46de5 Revert back to a machinearch (really cputype) of mips. Put ENDIAN back. 2000-12-03 07:05:21 +00:00
matt c1dbeee6d0 Deal with lack of floating point on hpcmips, etc. 2000-12-03 06:04:50 +00:00
matt 866f93d61f Change arch from mips to mipsel/mipseb as appropriate. Nuke the ENDIAN
makeoption.  Key off MACHINE_ARCH for adding -EB/-EL to CFLAGS/AFLAGS/LD/
LINKFLAGS.
2000-12-03 05:30:31 +00:00
matt ecf6f5a91f Add a POST_STRIP_SYSTEM_LD_FLAGS for mipsco and pmax. 2000-12-03 04:52:38 +00:00
matt 5e67131b91 Start using a Makefile.mips. Use a combination of makeoptions and
Makefile.sgimips.inc which has sgimips specific stuff.
2000-12-03 02:07:04 +00:00
tsutsui 936191481d Prepare cpu_exec_ecoff_probe() for mips which just returns ENOEXEC,
as per discussion on tech-kern.
2000-11-27 13:25:24 +00:00
soren a5dad0db13 Correct a few cpu/fpu ids. 2000-11-27 06:38:54 +00:00
nisimura fdfe3556de Use only one TLB entry to wire down process's USPACE since it's
now guranteed to be aligned on 8KB boundary in kernel virutal
address.  Retain one more free TLB entry.
2000-11-27 06:37:32 +00:00
chs b5142d6841 increase PAGER_MAP_SIZE to 16MB and move it to uvm_pager.h
since the alpha and mips pmaps use it.
2000-11-24 22:41:38 +00:00
soren 4927de268a Adjust for p_emul change. 2000-11-21 02:26:07 +00:00
jdolecek baae0324b9 restructure struct emul and execsw, in preparation to make emulations LKMable:
* move all exec-type specific information from struct emul to execsw[] and
  provide single struct emul per emulation
* elf:
  - kern/exec_elf32.c:probe_funcs[] is gone, execsw[] how has one entry
    per emulation and contains pointer to respective probe function
  - interp is allocated via MALLOC() rather than on stack
  - elf_args structure is allocated via MALLOC() rather than malloc()
* ecoff: the per-emulation hooks moved from alpha and mips specific code
  to OSF1 and Ultrix compat code as appropriate, execsw[] has one entry per
  emulation supporting ecoff with appropriate probe function
* the makecmds/probe functions don't set emulation, pointer to emulation is
  part of appropriate execsw[] entry
* constify couple of structures
2000-11-21 00:37:49 +00:00
thorpej cb38ab39ab We use 4K pages on MIPS systems (see mips_param.h), so override
PAGE_SIZE and friends to be compile-time constants.
2000-11-14 18:55:16 +00:00
thorpej e654e96593 Use 64-bit printf formats for paddr_t's (for arc port). 2000-11-09 06:02:40 +00:00
jeffs 196e858c40 Add mips_pagecopy/zero assembly loops for use by pmap_copy/zero_page*()
to allow the almost-64-bit compilation use ld/sd.
2000-10-31 23:39:24 +00:00
jeffs 50e0133709 At the end of pmap_zero/copy_page() use hit instead of index op when
running with multi-way caches.  Since we know the ops will mostly
hit as we just dirtied those lines a single hit op is cheaper than
an index op for each way.
2000-10-31 23:16:31 +00:00
jeffs 5ca84b9d89 Add MIPS3_NO_PV_UNCACHED option to handle virtual coherency issues by
only allowing one mapping at a time instead of mapping uncached.  Done
by removing conflicting mappings from the pmap when entering a new
mapping.  UVM will remember and re-fault the requested page when needed
for the original mapping.  Originally done to support our internal machine
that does not support uncached memory completely.  Not enabled by default
currently.  It may make sense to try on the cobalt or sgi ports.
2000-10-31 22:46:35 +00:00
jeffs 11ef576801 Add mips_indexof() macro to make code for checking the cache index
easier to read.
2000-10-31 21:21:10 +00:00
shin 1ddfbf7e96 fix cp0 hazard.
R4000 requires 3 nops between tlbr and dmfc0.
2000-10-29 08:01:29 +00:00
castor 2a04de9c03 In mips3_TBIS(va) do not invalidate the other half of the JTLB entry if
the page is wired down.  Flushing both halves of a wired TLB entry resulted
in hangs when in programs called for and released kernel memory
soon after being invoked.  In particular, we see this when single-stepping
a process using GDB.

It would be better if we could arrange to use both halves of the TLB
entry for the PCB, but for some reason we frequently end up with things
on an odd page boundary.
2000-10-24 03:23:19 +00:00
jeffs ade1f640e1 Go to to splhigh() in trap when panicing before calling debugger as break
handling does.
2000-10-23 05:49:05 +00:00
jeffs bdbb241be6 Fix race between pmap_enter() and pagedaemon. If we are low on memory and
pmap_enter() cannot allocate the segmap return failure if PMAP_CANFAIL
instead of sleeping.  Otherwise panic.  Both alpha and i386 do this.  Do
not pmap_enter_pv() until after this is done so the data structures are
not partially allocated.  This should prevent pmap_page_protect() from
getting stuck when called from pagedaemon.
2000-10-10 20:39:42 +00:00
nisimura 778081cbf4 Add mtc0 insn to load TX3900 config register value to determine Dcache size. 2000-10-09 10:14:23 +00:00
nisimura 89e5c346a4 mips1_ConfigCache() has gone. 2000-10-09 07:33:31 +00:00
cgd 59706f1322 clean up and consistency for CP0 Count, Compare, Wired, and Config
access function names and prototypes.
2000-10-05 02:36:44 +00:00
cgd b1b364243d always have to declare cpu_arch and the related constants (since setting
it isn't conditionalized).  (d'oh!)
2000-10-05 02:13:14 +00:00
cgd 7fefa594f7 add two blank lines 2000-10-05 01:17:20 +00:00
cgd 36123017cb nuke mips3_clearBEV(). There's really no point in coding a
special-purpose assembly routine for things like this.
2000-10-05 01:06:06 +00:00
cgd 3f1d3c3066 tweak cpu_arch. Eliminate all direct checks of it (making them
use the macro CPUISMIPS3 -- which is badly misnamed), and set it
from #defines named CPU_ARCH_N (where N is 1..5, 32, 64).
2000-10-05 00:52:59 +00:00
cgd e9e1084ea3 rename mips_read_causereg -> mips_cp0_cause_read. nuke prototype
for mips_read_statusreg (which was apparently never implemented).
Provide prototypes and implementations for mips_cp0_cause_write,
mips_cp0_status_read, and mips_cp0_status_write.  (Writing can, of
course, be quite dangerous.)
2000-10-04 22:44:01 +00:00
cgd 8b8afc8d07 the generic MIPS code doesn't even play at doing anything useful
with a MIPS4 option at this point -- all the code except for one single
spot is conditionalized with MIPS3.  So, don't even pretend about
MIPS4 for now, until it all gets cleaned up.
2000-10-04 21:41:47 +00:00
cgd 13eb329ef1 provide indicators of a few more things that might go in opt_cputype.h 2000-10-04 21:31:06 +00:00