revisions have, as discussed on the soekris-tech mailing list a
while ago, whereby one can experience excessive recieve erros when
using < 30m cables. The patch detects overflow in a DSP filter
parameter, and corrects it by writing a known good value.
- add pccbb_attach_hook in pccbbattach for MD initializations.
- omit arithmetics to bus_space_handle_t.
- remove use of IST_LEVEL; not defined on sparc64 and unused.
We only support legacy (i.e. PCI IDE compatible) mode, for now. Also
note that DMA is disabled for rev 0 chips unless explicitly enabled
with PCIIDE_I31244_ENABLEDMA.
so make driver match it
while here, also make the driver match 'Intel PRO/100 VM with
82562EM/EX (CNR) PHY', with anticipation it would work fine too
activate the resume and dynamic standby bug workaround for these; might
not be necessary (not confirmed to be needed), but better safe than sorry
Adresses PR kern/20689
This fixes the floppy access problem on some hardware.
Problem reported by Miroslav Kure via Jason Wright <jason [at]
thought [dot] net> of OpenBSD. Thanks.
Fix from ALSA driver; although this setting is undocumented but
according to Jaroslav Kysela <perex [at] suse [dot] cz> of ALSA,
there's no error reported so far.
Changes since last import:
. lots of whitespace cleanups
. typo fixes (e.g. hz, compatibilty)
. fix brightness ioctl return value
. wait for int ready using DELAY() instead of tight loop
require that the DMA receive buffers be aligned. The driver was
deliberately mis-aligning by 2 bytes, to force the layer-2/3
headers to 32-bit alignment.
Workaround: if chip is a 5701, and is in PCI-X mode, leave the DMA
buffers aligned. If the host CPU requires alignment, copy the buffer
after reception to force aligment.
Tested on an i386 in PCI-X bus, with __NO_STRICT_ALIGNMENT forced off.
Patch and comments reworked to minimize drift from
FreeBSD if_bge.c rev 1.14.
ram for using TBI, versus MII/GMII.
FreeBSD commit log and versions:
Obtain the media type from the shared memory and only use the eeprom
as a fallback.
if_bge.c: rev 1.30
if_bgereg.h: rev 1.13
Thanks to Paul Saab @mu.org.
as I submitted in PR kern/18093. Some of the patch needs refinement.
Also, only the ADC recording source is supported, because the other
sources are probably much less useful and the implementation isn't
trivial.
as bus_dmamem_alloc_range() is missing we use the ISA dma tag on i386.
The iorange for the dma registers now gets allocated near the used range.
Chances are high, that this range is valid on this PCI bus.
This one is really ugly :-)
Approved by: Lennart Augustsson <augustss@netbsd.org>
Put in code that, if enabled, makes *my* copper Sundance TI cards work-
promiscuous mode is needed for this for now. The default is to have this
off until I or somebody figures out what is broken- I think it's stuff
with the Marvell PHY.
malloc types into a structure, a pointer to which is passed around,
instead of an int constant. Allow the limit to be adjusted when the
malloc type is defined, or with a function call, as suggested by
Jonathan Stone.
Such RAID controllers are actually just IDE controllers with a BIOS that
can create RAID volumes and write the configuration info to config blocks
on the disks. The BIOS can do I/O to these volumes, and the OS must
understand the config blocks and implement RAID in software in order to be
able to use these volumes.
Only SPAN (simple concatenation) and RAID0 are supported at this time,
and writing back config blocks is also not supported at this time. Currently,
only the Promise configuration scheme is supported, although supporting
the Highpoint scheme should not be too difficult.
In any case, this is sufficient to use the Promise RAID0 volume (thus
preserving the win2k AS installation) on this new Intel server I have.
Thanks to Soren Schmidt for doing the work in FreeBSD; it made this
task much easier. The config block parsing code is adapted from his
work.
IDE controllers, which are more-or-less compatible with the
AMD controllers.
XXX Need to determine the correct timing value for the nForce2
XXX at Ultra133, so we cap it at Ultra100, for now.
Add cpp definitions for the DMA control register fields needed for
5703/5704 configuration on PCI-X.
Add softc copy of internal"local control" register clobbered by reset.
quirk on all 5700 revision B devices. (These fixes have not been
tested against NetBSD recently; committing the fix and the enable separately
gives us flexibility about which fixes get pulled into the NetBSD-1.6 branch.)
* Add support for 5704C dual-channel chip with integral copper PHY (tested)
and 5704S dual-channel SERDES/TBI gbic (untested). Add PHY DSP patch
for 5704.
* Update PHY DSP-code patch for bcm5401 to match latest Linux driver.
* Add PHY DSP-code patch for 5703 (untested).
* Update onchip buffer tunables to recommended values from Linux drivers.
* Disable MWI access. This chip family cannot hanlde PCI stalls
in the middle of an MWI burst. The driver has heuristics to detect PCI
line size, but under load, some PCI bridges may force stalls which
the attach-time heruistics do not catch. Some PCI bridges never
do this, so maybe it should be a tunable option.
* bcm5700 rev Bx chips have a race condition, where updating the
Tx producer pointer goes un-noticed by the chip. Workaround is to
write the new producer-pointer value twice.
* bcm5700 chips rev Bx wedge up if given DMA descriptors of
eight bytes or less. Once hit, only reovery is a watchdog timeout/reset.
If the offending packet is retransmitted, the chip will wedge again...
Check for teeny fragments in a Tx request, and either fold the
teeny chunk residue into an adjacent mbuf, or m_dup the entire buffer.
(NB: quirk not yet enabled; in-place folding tested only on FreeBSD.)
* Add workaround for revision Bx bcm5700: chip bugs in decoding
of PCI register writes may leave the hardware in (partial) powersave state,
such that writes to "indirect" registers do not work.
Explicitly force chip into D0 state at attach time.
* Accessing PHY registers with the bge chip in autopoll mode, when
link-state is the process of changing, may cause the bge chip to
assert PCI errors. Workaround: when doing miibus register access,
save autopoll state, disable around access, and restore autopoll state.
NB: issuing PHY resets may give a window where the problem still occurs.
* Increase Tx interrupt-coalescing thresholds, to reduce Tx-done interrupts.
auich_set_rate() modified audio_params::sample_rate to actual
sample rate though auich_set_params() rejected sample rates
other than some specific rates. For example, setting 8000Hz
with auich_set_params() modified sample_rate to 7998Hz in the
case of overclocked AC97 codec, and calling auich_set_params()
again returned with EINVAL because sample_rate was 7998Hz and
auich_set_params() rejected 7998Hz.
For now, auich_set_params() never modify audio_params::sample_rate.
Uploaded scripts work better if they are little endian, as the
card's engine expects, so convert to le first.
Also clean up attach routine a bit (use pa_id and PCI_REVISION
instead of fetching it ourselves).
This makes the driver work on my macppc G4, it can decode and
display video and tuner input. Sound does not seem to work, but
this may be my wonky formac bktr-for-macintosh card.
- Windows put the chip in suspended mode, make sure we unsuspend
it. 1.43, by Takefumi SAYO <stake@po.shiojiri.ne.jp>
- Detect the revision of the Rhine chip we're using, and force reset
when the chip supports it. 1.65, by silby@freebsd.org
16-bit mono recording seems to work OK. 16-bit stereo recording
is missing the left channel for reasons unknown, fixes welcome.
8-bit recording still unsupported.
and avoid using MD myetheraddr() function.
This makes the driver MI, and closes PR kern/13797.
The PCI HME is a PCIO chip, which is composed of two functions:
function 0: PCI-EBus2 bridge, and
function 1: HappyMeal Ethernet controller.
The Ethernet address is (expected to be) in the PCI FCode PROM connected
to the EBus bridge (function 0) of the device.
Since the HME is on function 1, some magic is used to access to the PROM.
We don't have MI EBus driver since no EBus device exists (besides the
FCode PROM) on add-on HME boards. The ``not configured'' message for
function 0 is what is expected.
The SPARC case is currently unchanged. It needs interaction with OpenBoot.
card contains only one clock, which is already used by the other
DAC. The FM DAC can handle a few fixed-frequency choices.
thanks to Matthew Green for testing
FreeBSD, with cleanup/KNF by me.
Note: These chipsets are not well supported by the i810 driver in
NetBSD's in-tree xsrc (based on XFree86 4.2.1 at this time). However,
the driver works perfectly using bleeding-edge XFree86-current on my
Omnibook's i830MG with these agp changes.
isochronous reception routine for IEEE 1394 OHCI (fwohci). The
transmission part is under construction.
The minimum configuration options for this feature are:
# IEEE 1394 (i.LINK)
fwohci* at pci? dev ? function ?
pseudo-device fwiso 1
This change makes the driver work properly for the following card,
which used to function a bit weird:
eap0 at pci0 dev 10 function 0: Ensoniq CT5880 CT5880C (rev. 0x02)
eap0: interrupting at irq 9
eap0: TriTech TR28602 codec; no 3D stereo
pdc202xx_setup_channel, pdc20268_setup_channel:
Properly compute the address of the DMA control register for channel 1.
I think the controllers ignore these bits, I suspect it's only there so that
the BIOS can tell the OS is has configured DMA, but better be correct.
Thanks to Alexander Yurchenko for pointing this out.
> Remove an entry for AMD PCNETS_PCI.
>
> AMD Am79C974 PCnet-SCSI Ethernet and SCSI conrtoller is
> a multi-function PCI device which has two device IDs
> of Am53C974(PCscsi-PCI) and Am79C970(PCnet-PCI),
> and there is no its own ID.
AMD Am79C974 PCnet-SCSI Ethernet and SCSI conrtoller is
a multi-function PCI device which has two device IDs
of Am53C974(PCscsi-PCI) and Am79C970(PCnet-PCI),
and there is no its own ID.
tron