Commit Graph

1232 Commits

Author SHA1 Message Date
simonb c5d34b4371 Remove the number of TLB entries for different rx39 CPUs - this info
is in the table in mips_machdep.c now.
2002-03-05 16:02:48 +00:00
simonb c6bcfb2589 Add support for MIPS32 and MIPS64 architectures:
- Move away from using CPUISMIPS3; use MIPS_HAS_R4K_MMU instead.
 - Bump the Sysmap size a little for large-memory machines.
XXX: still need work, especially in pmap_procwr().
2002-03-05 16:01:25 +00:00
simonb 0f9c00fc2e Add support for MIPS32 and MIPS64 architectures:
- Move away from using CPUISMIPS3; use MIPS_HAS_R4K_MMU instead.
 - ANSIfy.
2002-03-05 15:57:20 +00:00
simonb fa9c08ab16 Remove HPCMIPS_FLUSHCACHE_XXX debug code.
Remove old unused exception frame unwind code.
Change a MIPS3 check to a MIPS3_PLUS check.
ANSIfy.
2002-03-05 15:55:41 +00:00
simonb 278bfc1c02 Add support for MIPS32 and MIPS64 architectures:
- move away from using CPUISMIPS3; use MIPS_HAS_CLOCK instead.
2002-03-05 15:54:33 +00:00
simonb 351c1c16a6 Add support for MIPS32 and MIPS64 architectures:
- Use a table-driven CPU detection algorithm instead of multiple
   case statements.
 - Add MIPS32/64 feature detection using the architected CP0 registers
   (from Broadcom Corp).
 - Call MD mips_machdep_cache_config() function if
   __HAVE_MIPS_MACHDEP_CACHE_CONFIG is defined - used to set up the
   L2 cache on some ports.
2002-03-05 15:53:00 +00:00
simonb ba8e2e82e4 Add support for MIPS32 and MIPS64 architectures:
- Remove all mmu-related code that may use 32 register on mips32-style
   implementatios and move them to mipsX_subr.S - which is then included
   from mips{3,32,64,5900}_subr.S with various control defines enabled.
 - Remove local cache instruction flags
 - Add badaddr64 (from Broadcom Corp).
2002-03-05 15:50:59 +00:00
simonb 9ed4fd257f Change a MIPS3 check to a MIPS3_PLUS check.
XXX: I'm not 100% sure of the intent of this code - it would seem that
 it needs a run-time check of CPU ISA to be completely correct...
2002-03-05 15:48:31 +00:00
simonb d62813603c Check userland address and address alignent as two separate checks.
Fix for when mips_reg_t is 64-bits.
ANSIfy.
2002-03-05 15:46:51 +00:00
simonb fe86ad150e Change MIPS3 checks to MIPS3_PLUS checks (XXX - still bogus!). 2002-03-05 15:44:40 +00:00
simonb c9a3bd8900 Add support for MIPS32 and MIPS64 architectures:
- Move away from using CPUISMIPS3; use MIPS_HAS_R4K_MMU instead.
 - Add a command to dump cp0 state.
2002-03-05 15:43:25 +00:00
simonb 9b785c48f3 Cache ops for MIPS32/64 cpus. 2002-03-05 15:42:50 +00:00
simonb 0446046fde Add MIPS32/64 cache setup code (from Broadcom Corp). 2002-03-05 15:42:21 +00:00
simonb cae6e0e516 Prototypes for MIPS32/64 cache ops. 2002-03-05 15:41:48 +00:00
simonb 0ff59237ca Change a MIPS3 check to a MIPS3_PLUS check (XXX - still bogus!). 2002-03-05 15:41:14 +00:00
simonb 01422aae5c Add support for MIPS32 and MIPS64 architectures:
- move away from using CPUISMIPS3; use MIPS_HAS_CLOCK instead.
2002-03-05 15:40:10 +00:00
simonb 1d05db445d Add support for MIPS32 and MIPS64 architectures:
- Move away from using CPUISMIPS3; use MIPS_HAS_R4K_MMU instead.
2002-03-05 15:39:31 +00:00
simonb 934c4ba555 Add support for MIPS32 and MIPS64 architectures:
Remove the unused PSL_USERCLR and BASEPRI macros.
2002-03-05 15:38:33 +00:00
simonb b255c47737 Add support for MIPS32 and MIPS64 architectures:
Better cache coherency attribute macros (from Broadcom Corp).
2002-03-05 15:37:32 +00:00
simonb f38d391749 Add support for MIPS32 and MIPS64 architectures:
- Add mips32 and mips64 locore function prototypes.
 - Add mips3_lw_a64() and mips3_sw_a64() for access data at any
   64bit address (from Broadcom Corp).
 - Add Broadcom and Sandcraft CPU company ids.
2002-03-05 15:36:51 +00:00
simonb 2fab526863 Add support for MIPS32 and MIPS64 architectures:
- Add XKPHYS macros (from Broadcom Corp).
 - Add some r5900 register bit definitions.
 - Add extra exception vector addresses for mips32/mips64 and r5900.
 - Make the mips cp0 register definitions available from both asm and C.
 - Add some Alchemy and Sandcraft CPU ids.
 - Add r3000, tx39xx and r4x00 CPU revision ids.
 - Remove defines for the number of TLBs on some CPUs.
2002-03-05 15:35:22 +00:00
simonb 60fe625bd0 Add support for MIPS32 and MIPS64 architectures:
- Clean up (somewhat) mips1 vs mips3+ configuration.
   XXX:  this is still quite messy.
 - Add cpu frequency info to struct cpu_info.
 - ANSIfy.
2002-03-05 15:34:04 +00:00
simonb ef0fcacb94 ANSIfy. 2002-03-05 15:12:58 +00:00
simonb 8070cbd848 Add 4way 16/32-byte-line cache op primitives. 2002-03-05 14:32:26 +00:00
simonb e8e49d677b Don't explicitly depend locore_*.S and fp.S on assym.h - this is done
for all .S files in /sys/conf/Makefile.kern.inc.
2002-03-05 14:28:31 +00:00
simonb 7bd5992f7a Fix for when we have 64 bit registers enabled for userland (but still
using the o32 API).
2002-03-05 14:23:50 +00:00
simonb 4a931bedb8 KNF whitespace. 2002-03-05 14:21:32 +00:00
simonb 59f53aab95 The 64-bit safe, ILP32 o32 model is safe with the current stdarg
implementation.
2002-03-05 14:18:12 +00:00
simonb 836b7ec262 Include <machine/cdefs.h> to select 32/64bit APIs. 2002-03-05 14:17:16 +00:00
simonb b2fb45331b ANSIfy. 2002-03-05 14:08:43 +00:00
simonb 58faa5f0ca Clean up #ifdef checks a little. 2002-03-05 14:08:07 +00:00
simonb 6f0fb25121 Don't need to declare phys_map - it is declared in <uvm/uvm_extern.h>. 2002-03-04 02:43:22 +00:00
simonb 4324f37586 Use "#define<tab>". 2002-02-28 03:17:23 +00:00
christos e8116a8f5b - Use DEV_ constants, instead of documenting the numbers!
- Delete cdev_decl(mm); where appropriate, and other hand-crufting [hi powerpc!]
2002-02-27 01:20:51 +00:00
simonb e19a9be04b Note that "addu $x, $y, $0" is a "move" only in 32-bit mode.
XXX: need to revisit this.
2002-02-22 16:18:36 +00:00
simonb 2d8577fb83 Clean up some rampant code duplication wrt ieee number handling:
- Add alignment-safe double and float unions.
 - Use the above for the __infinity and __nan constants on all
   architectures that use the standard ieee754 representation of
   those constants.
 - Add a single copy of various ieee754 math functions (frexp, isinf,
   isnan, ldexp and modf) that had numerous duplicates among the
   arch-specific directories.
 - Use the above functions on all architectures where the generic C
   versions where used.  Architectures that had local assembly
   routines are untouched (for those functions only).
2002-02-19 13:08:12 +00:00
simonb 4a188395df Make the ddb_regs declaration an extern in db_machdep.h and declare it on
db_interface.c.
2002-02-15 07:32:34 +00:00
thorpej 90544559d3 Don't put `frompc' into a0 in the delay slot of the __mcount
call; `jal __mcount' might be expanded by the assembler, and
thus a bogus `frompc' value could be passed.
2002-02-05 07:12:20 +00:00
manu 97db5a818c Added errno translation for non native OSes emulation (IRIX, Linux, Ultrix) 2002-02-02 20:28:59 +00:00
uch 715eb97754 remove unused variable. 2002-01-30 16:10:08 +00:00
uch e3ba66bfd4 move TX39 specific cache configuration code to cache.c 2002-01-30 16:09:29 +00:00
shin 69d0f55255 add VR4131 cache-op bug workaround code.
we can't use Hit_WriteBack_Invalidate.
2002-01-19 04:25:36 +00:00
soren 07e21646eb Options MIPS3_5200 and MIPS3_L2CACHE_PRESENT are gone. 2002-01-14 19:07:16 +00:00
enami 5c12da5b4a Define new macro to access FSR register and use it. 2002-01-12 01:40:36 +00:00
enami 16fc46b962 Access FSR register correctly in struct fpreg.r_regs[].
This fixes sshd (actually, libcrypto) failure with new-toolchain.
2002-01-12 01:37:08 +00:00
thorpej 94f30b739f Add the BONITO_ICU_RETRYERR bit. 2002-01-09 02:35:29 +00:00
thorpej 4928315412 Update copyright. 2002-01-09 00:44:06 +00:00
thorpej d25ffb2822 Add code to manipulate the BONITO I/O Buffer Cache. 2002-01-09 00:43:38 +00:00
shin a0a83ff5d4 fix pasto.
s/trunc_line/trunc_line16/
2002-01-07 07:43:52 +00:00
takemura eef721771a Modify only K0 bits and save other bits. (HPCMIPS_L1CACHE_DISABLE) 2002-01-04 09:26:39 +00:00
uch e4130f57f1 _intr_suspend and _intr_resume declarations are moved to intr.h. 2002-01-02 12:36:20 +00:00
shin b7e3f7d6e3 R4000/R4400 always detects virtual alias as if
primary cache size is 32KB. Actual primary cache size
is ignored wrt VCED/VCEI.
2001-12-28 04:06:06 +00:00
shin f15b256063 check if curproc is invalid, and do panic.
otherwise, we can't useful backtrace.
Ex. address error in interrupt handler.
2001-12-28 02:13:14 +00:00
shin ae12ee76a0 add #ifdef DEBUG around VCED_count etc. 2001-12-27 22:55:46 +00:00
shin 606f00a905 split VCED and VCEI. 2001-12-27 04:19:17 +00:00
shin d00d2e4bcb simplify VCED processing.
just write back and invalidate secondary cache line and fetch data again.
2001-12-27 04:03:37 +00:00
takemura 490f777a1f Added Vr4131 support. 2001-12-23 13:10:46 +00:00
thorpej 51535d4bf5 Add support for dumping ELF-cormat core files. 2001-12-09 23:05:56 +00:00
atatat b45c51b1fc Roll the rest of the ports over to the new MI kernel build machinery.
Any problems reported by testers have been fixed, and massive
cross-compiling of kernels has shown that any problems that remain
with actually building kernels are not related to this.
2001-12-09 05:00:40 +00:00
manu 342f5317b0 Added IRIX signal trampoline 2001-12-08 11:15:43 +00:00
uch 2c8098281b TX39, R5900 cache configuration. 2001-12-02 10:37:25 +00:00
manu fd6a281221 Added twomissing SYSCALL_SHIFT for indirect syscall through SYS_syscall 2001-12-02 08:28:18 +00:00
manu 55c08f5ede Back out the copy of theses files to userland 2001-11-28 20:13:34 +00:00
manu fa1e4588d9 We need to copy new SVR4 header files to /usr/include/sys... 2001-11-28 12:13:49 +00:00
manu f73e64b4be Added support for COMPAT_IRIX 2001-11-28 11:54:15 +00:00
lukem ecb81c3f6d - convert usage of "defopt" to "defflag" where the relevant option does
not support a value (e.g., it's to be used as "options FOO" instead of
  "options FOO=xxx"). options that take a value were converted to
  defparam recently.
- minor whitespace & formatting cleanups
2001-11-28 10:21:10 +00:00
nisimura 9f8ca586ad Fix a small typo in comment. 2001-11-28 08:49:19 +00:00
manu 12c949a188 Added COMPAT_IRIX (being developped, not functionnal at that time) 2001-11-26 21:38:41 +00:00
shin 3dfc0ff3ab fix pasteo. 2001-11-26 13:16:17 +00:00
uch 6bd02d8e33 add #ifndef _LOCORE. 2001-11-23 15:48:40 +00:00
tsutsui d8879382cf Add 32B/l L1 D/I-cache ops for newer ARC machines. 2001-11-23 06:21:49 +00:00
simonb 944346b889 KNF, ANSIfy.
Change print_addr() to take an db_addr_t argument instead of a long.
2001-11-22 06:58:03 +00:00
simonb 973ad566f7 Update the CP0 register names.
Make some tables line up nicely.
Make print_addr() static.
2001-11-22 06:00:31 +00:00
manu 675946fd1c Fixed the Linux signal trampoline and linux_sys_sigreturn(). Linux signal
delivery now seems fully functionnal.
2001-11-20 21:37:50 +00:00
lukem 03aef4723c cleanup:
options SPACE TAB
	makeoptions TAB
	psuedo-device TAB
	remove trailing whitespace
	replace multiple spaces -> tabs
	options "FOO" -> options FOO
	options "FOO=bar" -> options FOO=bar
	options "FOO=\"bar\"" -> options FOO="\"bar\""
2001-11-20 12:56:17 +00:00
shin 07356ec733 improve r4k_sdcache_XXX_generic(). 2001-11-20 06:32:21 +00:00
thorpej 6e69c4e62c Add mips_dcache_align and mips_dcache_align_mask variables that
contain information suitable for allowing other parts of the kernel
to determine if a memory region is aligned to the largest data cache
line size present in the system.

Add a mips_dcache_compute_align() function which must be called whenever
one of the data cache line size variables is changed, in order to
compute mips_dcache_align and mips_dcache_align_mask.
2001-11-19 01:28:07 +00:00
thorpej 4609c9fbb4 r4k_sdcache_wbinv_range_index_32(): fix a typo (16 -> 32). 2001-11-18 18:48:55 +00:00
thorpej e6cab2e799 Add 128b/l L2 cache ops. 2001-11-18 18:46:20 +00:00
simonb 0f3507ed9c White space nit. 2001-11-18 03:47:53 +00:00
soren 662f877587 MAXSLP is defined to be a machine-independent scheduling parameter,
so move it into sys/param.h.
2001-11-15 18:06:11 +00:00
thorpej bd15cfaed8 Merge the thorpej-mips-cache branch onto the trunk. This is an
overhaul of how caches are handled for NetBSD's MIPS ports.
2001-11-14 18:26:21 +00:00
thorpej af66038f73 Merge the thorpej-mips-cache branch onto the trunk. This is an
overhaul of how caches are handled for NetBSD's MIPS ports.
2001-11-14 18:15:10 +00:00
simonb 1143123ee5 Fix pasto in a comment. 2001-11-12 11:12:16 +00:00
thorpej 47514a31be Remove unneeded declarations of the db_machine_init() function. The
ARM ports are the only ones that actually have one, and it is about
to change.
2001-11-09 06:52:23 +00:00
tsutsui 882785d057 Cast pa values to u_long in DEBUG printfs for _MIPS_PADDR_T_64BIT ports.
XXX should use unsigned long long format?
2001-11-04 14:07:13 +00:00
chs fa6e18a029 in pmap_extract(), detect unmapped users addresses too. 2001-11-01 07:37:36 +00:00
thorpej e8ee04475d - Add a new vnode flag VEXECMAP, which indicates that a vnode has
executable mappings.  Stop overloading VTEXT for this purpose (VTEXT
  also has another meaning).
- Rename vn_marktext() to vn_markexec(), and use it when executable
  mappings of a vnode are established.
- In places where we want to set VTEXT, set it in v_flag directly, rather
  than making a function call to do this (it no longer makes sense to
  use a function call, since we no longer overload VTEXT with VEXECMAP's
  meaning).

VEXECMAP suggested by Chuq Silvers.
2001-10-30 15:32:01 +00:00
shin 4843675231 fix virtual alias problem in pmap_copy_page().
to eliminate virtual alias, source page should also be flushed.
fixes PR/13587.
2001-10-27 05:44:45 +00:00
shin e003f33738 remove " in assignment of ENDIAN.
fixes mipseb link breakage.
2001-10-26 08:25:54 +00:00
jmc 6d536163de Change defaults for kernel compiles. Default all to USETOOLS?=no and have
the etc Makefile override that by putting USETOOLS into $.MAKEOVERRIDES
This way the default for kernel compiles is still to use the installed
toolchain instead of depending on $TOOLDIR. $TOOLDIR can be used by
simply adding USETOOLS=yes to the command line as usual.

Adjust each ports template to set the default no setting and also pull in
bsd.own.mk if they weren't already to ensure they'll build correctly
with the new toolchain setup.
2001-10-26 06:45:33 +00:00
thorpej 90a2bc2cf7 For MIPS kernel Makefiles, don't set ENDIAN in std.${MACHINE}. Instead,
explicitly set MACHINE_ARCH to the appropriate thing.  Makefile.mips will
then set all of the internal variables it needs to accordingly.
2001-10-23 20:40:00 +00:00
thorpej 2c5ebcddfb Use MACHINE, not TARGET_MACHINE. 2001-10-23 18:57:32 +00:00
uch d8c8db85ef R5900 support.
COP0_SYNC
	In R5900 mtc0, tlbr, tlbp, tlbwi, tlbwr must be followed by sync.p.
	if defined MIPS3_5900, COP0_SYNC is defined as sync.p. else nothing.
 IPL_ICU_MASK
	mask interrupt directly ICU instead of SR.IM.
	I've added this feature to support software interrupt for R5900.
	and this option may be useful for platform which has cascaded ICU.
2001-10-16 16:31:32 +00:00
simonb 6048ce9247 Use a separate variable (${KERNLDSCRIPT}) for the name of the kernel
ld script, so it can be used in other places.
2001-10-08 10:14:20 +00:00
simonb 4471b94432 This Makefile.inc is used for building LKMS - add the standard MIPS
kernel compile flags as well as "-mlong-calls" so that calls from the
LKM in KSEG2 work to the kernel in KSEG0.

MIPS LKMs now build and can be loaded with the right Magick command line
args to modload(8).  Changes to modload coming...

Thanks to Chris Demetriou for pointing out the -mlong-calls gcc option
that had been staring me in the face all along.
2001-10-05 15:36:46 +00:00
simonb 1f8636506e Use ".-include" instead of the ".if exists(...) ..." dance. 2001-10-05 15:14:18 +00:00
simonb bc2ec5e553 Use a single ldscript instead of separate scripts for either endianness;
use command line parameters to ld(1) instead to set the endian format.
Clean up some endian decisions in mips/conf/Makefile.mips.
Wrap some long lines.
2001-10-05 05:03:27 +00:00
manu 2d16421460 Moved COMPAT_LINUX config stuff from arch/sgimips to arch/mips, so that it's
available on all Mips ports.
2001-09-23 19:45:41 +00:00
manu 151b90c898 Added Linux emulation support to Mips port 2001-09-22 21:29:20 +00:00