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515 Commits

Author SHA1 Message Date
gmcgarry
cc4037a913 Overhaul the emulation facility. We do this by: 
- accumulating all emulation code (including floating-point) in one place
- steal MachFPInterrupt() back from SOFTFLOAT for use only with interrupts
  and traps from *real* FPUs
- introducing MachEmulateInst() as a common dispatch point for all
  emulated instructions
- cleaning up emulation dispatch in trap()

Also, while we're here, implement MIPS2 LL/SC/SYNC emulation for MIPS1.

Tested on r3k with and without SOFTFLOAT enabled.
 2002-07-06 23:59:18 +00:00
simonb
7471732325 Add the 20Kc processor ID. 2002-06-27 03:43:45 +00:00
simonb
d4068eac65 Add 64MB and 256MB tlb page masks. 2002-06-24 05:46:47 +00:00
manu
d0c5097f05 Typo 2002-06-23 20:36:36 +00:00
simonb
db50a069f8 Remove an ELF-related comment that isn't needed any more. 2002-06-05 06:02:52 +00:00
simonb
2100183aff For the CP0 status register bit definitions- add the MX, PX and NMI bits 
and rename TLB_SHUTDOWN and SOFT_RESET to TS and SR (the abbreviations
in the MIPS documentation).

XXX: this file really needs to be cleaned up one day...
 2002-06-05 05:56:48 +00:00
simonb
9cc65a96d0 3 ports are now using the reciprocal count divisor code now, move it 
to <mips/cpu.h>, and add MIPS_SET_CI_RECIPRICAL and MIPS_COUNT_TO_MHZ
macros to use it.
 2002-06-04 05:42:41 +00:00
simonb
8b4906e391 Add prototypes for the 64-bit pagezero functions. 
Bracket some function prototypes with #ifdef/#endif.
 2002-06-03 01:51:05 +00:00
simonb
341ed8c0d3 Use CPU_MIPS_USE_WAIT and CPU_MIPS_NO_WAIT in the CPU table, and use 
the generic name "mips_wait_idle" for the old function that had both
rm52xx_idle and mipsNN_idle entry points.
 2002-06-01 13:45:45 +00:00
simonb
cf5f852d1c Standardise on the name "MIPS_SR_BEV" instead of a couple of different 
#defines for the same status bit.
 2002-06-01 12:27:03 +00:00
simonb
5b5cc1ebb8 Add two new cpu capability flags: CPU_MIPS_USE_WAIT for CPUs that use a 
"wait" instruction based cpu_idle(), and CPU_MIPS_NO_WAIT for specific
CPUs that don't use this (applicable to mips32/64 mainly).
 2002-06-01 12:10:45 +00:00
thorpej
dada8613e1 Let machine-dependent code specify how to enumerate the bus. 
Currently, everyone uses pci_enumerate_bus_generic().
 2002-05-15 19:23:51 +00:00
simonb
ada33c9eac Oops, remove an #endif leftover from the previous change. 2002-05-13 06:11:52 +00:00
simonb
c790dd34b6 Add a comment after an #endif to match up with an #ifdef. 2002-05-13 04:15:40 +00:00
simonb
ee2264c945 All MIPS ports have been ELF for a long time (most since they were 
created); remove non-ELF assembly support.
 2002-05-13 01:39:17 +00:00
simonb
2d7c87ebfb Add a "CPU_MIPS_DOUBLE_COUNT" flag for CPUs where the cp0 count register 
ticks over at half the CPU clock speed, and set this flag for the known
CPUs with this behaviour.  Better names for this flag gratefully accepted!

Also adjust comment about known R4000/R4400 revisions.
 2002-04-05 01:22:16 +00:00
simonb
67fd901d75 Include 2way cache ops for mips{32,64} CPUs. 2002-04-03 03:51:00 +00:00
simonb
078e9477f0 Add prototype for badaddr64(). 2002-04-03 03:48:33 +00:00
simonb
267b8c65f5 Define all CPU types if _LKM is defined; fixes problems building LKM's 
as noted by FUKAUMI Naoki on port-mips.
 2002-03-19 00:53:46 +00:00
simonb
91785659ba Generic PCI/ISA machdep headers for mips; copied from the algor port. 2002-03-18 03:08:09 +00:00
simonb
e64d2d9708 Oops, balance #ifdef/#endif _KERNEL. 2002-03-18 01:01:54 +00:00
simonb
d9aac5ef07 Add generic MIPS bus_space and bus_dma headers; these are a straight 
split of the algor <machine/bus.h>.
 2002-03-18 00:32:21 +00:00
simonb
17162f3d40 Add R4400 reg 0x60 to the MIPS CPU table. 
From PR port-mips/15894 from Thilo Manske.
 2002-03-13 13:18:58 +00:00
uch
552fdb7e1b make this compile and work with MIPS3_5900. 2002-03-11 16:39:39 +00:00
simonb
78c9211fca Add a field for the reciprocal of the divisor delay for use by microtime. 2002-03-06 07:31:38 +00:00
simonb
f340c57568 Values related to the MIPS32/MIPS64 Privileged Resource Architecture 
(from Broadcom Corp).
 2002-03-05 16:07:10 +00:00
simonb
dd756c0ca5 Rename <mips/r5900/cpuregs.h> to <mips/r5900regs.h> and remove some 
content no longer needed.
 2002-03-05 16:04:57 +00:00
simonb
c5d34b4371 Remove the number of TLB entries for different rx39 CPUs - this info 
is in the table in mips_machdep.c now.
 2002-03-05 16:02:48 +00:00
simonb
cae6e0e516 Prototypes for MIPS32/64 cache ops. 2002-03-05 15:41:48 +00:00
simonb
0ff59237ca Change a MIPS3 check to a MIPS3_PLUS check (XXX - still bogus!). 2002-03-05 15:41:14 +00:00
simonb
01422aae5c Add support for MIPS32 and MIPS64 architectures: 
- move away from using CPUISMIPS3; use MIPS_HAS_CLOCK instead.
 2002-03-05 15:40:10 +00:00
simonb
1d05db445d Add support for MIPS32 and MIPS64 architectures: 
- Move away from using CPUISMIPS3; use MIPS_HAS_R4K_MMU instead.
 2002-03-05 15:39:31 +00:00
simonb
934c4ba555 Add support for MIPS32 and MIPS64 architectures: 
Remove the unused PSL_USERCLR and BASEPRI macros.
 2002-03-05 15:38:33 +00:00
simonb
b255c47737 Add support for MIPS32 and MIPS64 architectures: 
Better cache coherency attribute macros (from Broadcom Corp).
 2002-03-05 15:37:32 +00:00
simonb
f38d391749 Add support for MIPS32 and MIPS64 architectures: 
- Add mips32 and mips64 locore function prototypes.
 - Add mips3_lw_a64() and mips3_sw_a64() for access data at any
   64bit address (from Broadcom Corp).
 - Add Broadcom and Sandcraft CPU company ids.
 2002-03-05 15:36:51 +00:00
simonb
2fab526863 Add support for MIPS32 and MIPS64 architectures: 
- Add XKPHYS macros (from Broadcom Corp).
 - Add some r5900 register bit definitions.
 - Add extra exception vector addresses for mips32/mips64 and r5900.
 - Make the mips cp0 register definitions available from both asm and C.
 - Add some Alchemy and Sandcraft CPU ids.
 - Add r3000, tx39xx and r4x00 CPU revision ids.
 - Remove defines for the number of TLBs on some CPUs.
 2002-03-05 15:35:22 +00:00
simonb
60fe625bd0 Add support for MIPS32 and MIPS64 architectures: 
- Clean up (somewhat) mips1 vs mips3+ configuration.
   XXX:  this is still quite messy.
 - Add cpu frequency info to struct cpu_info.
 - ANSIfy.
 2002-03-05 15:34:04 +00:00
simonb
8070cbd848 Add 4way 16/32-byte-line cache op primitives. 2002-03-05 14:32:26 +00:00
simonb
59f53aab95 The 64-bit safe, ILP32 o32 model is safe with the current stdarg 
implementation.
 2002-03-05 14:18:12 +00:00
simonb
836b7ec262 Include <machine/cdefs.h> to select 32/64bit APIs. 2002-03-05 14:17:16 +00:00
simonb
b2fb45331b ANSIfy. 2002-03-05 14:08:43 +00:00
simonb
58faa5f0ca Clean up #ifdef checks a little. 2002-03-05 14:08:07 +00:00
simonb
4324f37586 Use "#define<tab>". 2002-02-28 03:17:23 +00:00
simonb
2d8577fb83 Clean up some rampant code duplication wrt ieee number handling: 
- Add alignment-safe double and float unions.
 - Use the above for the __infinity and __nan constants on all
   architectures that use the standard ieee754 representation of
   those constants.
 - Add a single copy of various ieee754 math functions (frexp, isinf,
   isnan, ldexp and modf) that had numerous duplicates among the
   arch-specific directories.
 - Use the above functions on all architectures where the generic C
   versions where used.  Architectures that had local assembly
   routines are untouched (for those functions only).
 2002-02-19 13:08:12 +00:00
simonb
4a188395df Make the ddb_regs declaration an extern in db_machdep.h and declare it on 
db_interface.c.
 2002-02-15 07:32:34 +00:00
thorpej
90544559d3 Don't put `frompc' into a0 in the delay slot of the __mcount 
call; `jal __mcount' might be expanded by the assembler, and
thus a bogus `frompc' value could be passed.
 2002-02-05 07:12:20 +00:00
shin
69d0f55255 add VR4131 cache-op bug workaround code. 
we can't use Hit_WriteBack_Invalidate.
 2002-01-19 04:25:36 +00:00
enami
5c12da5b4a Define new macro to access FSR register and use it. 2002-01-12 01:40:36 +00:00
uch
e4130f57f1 _intr_suspend and _intr_resume declarations are moved to intr.h. 2002-01-02 12:36:20 +00:00
shin
b7e3f7d6e3 R4000/R4400 always detects virtual alias as if 
primary cache size is 32KB. Actual primary cache size
is ignored wrt VCED/VCEI.
 2001-12-28 04:06:06 +00:00