overlap; don't require allocation from the dense extent if the PCI
memory address isn't mapped into dense space.
Also, make sure to return an error if a liner mapping is requested
and dense space is not available (not just not requested).
configuring w/o SIO broke compilation. I forget why, but there was at one
point (and may still be) a dependency between SIO and EISA. This change
just makes things compile sensibly again. It may make no sense to build
a kernel w/o sio in this case. I can't test this conveniently because I
haven't got a 4100 with a video card in it at the moment.
- Actually display the kn300 irq, not the MCPCIA irq, in the interrupt
string. Also, don't bother displaying device/pin on strays, since
it doesn't play will with shared interrupts that would happen due to
a PCI-PCI bridge.
- Shave a few more cycles out of the interrupt dispatch routine.
supposed to be Window 1, but a cut'n'paste error made it stomp over
Window 0, thus breaking ISA DMA. Fix this. (Confirmed to work with
floppy driver.)
While I'm here, do something I've been meaning to do for a while: change
Window 1 from a 1G at 2G to a 2G at 2G direct-mapped window, and add
a Window 2 of 1G at 1G SGMAP-mapped. Chain Window 2 to Window 1, and
use it as a fall-back for PCI DMA if the system has more than 2G of RAM.
The access is more efficient this way (and this was done in the interrupt
dispatch code, so some cycles are actually shaved), and gcc gets annoyed
when chars are used as array subscripts.
- Adjust for the fixed Rawhide console initialization.
- When mapping a PCI interrupt, don't always map device 1 to IRQ 16. Device
1 is only the internal 53c810 on MID 5, and is an invalid device number
on any other MID.
- Adjust for change mcpcia_config/mcpcia_softc structures.
- Nuke the kludgy linked list of mcpcia_softc structures. Instead, just
use savunit[v] to index into mcpcia_cd.cd_devs[] to find the MCPCIA
which has the stray interrupt.
- Some other minor cosmetic cleanup.
which holds state of the MCPCIA to which the console is attached.
- All MCPCIA info is now stored in the mcpcia_config structure; the
mcpcia_softc only contains a struct device and a pointer to one of these.
- If attaching the console MCPCIA, use the static configuration, else allocate
the substructure.
- Rename mcpcia_init() to mcpcia_init0(), and make it take a "mallocsafe"
argument.
- Implement a new mcpcia_init(), which looks for the MCPCIA which has the
EISA bridge attached. Initialize this MCPCIA as the console MCPCIA (the
console on the Rawhide is only allowed on this MCPCIA; firmware rule).
- Eliminate the kludgy linked listed of mcpcia_softcs. Just use mcpcia_cd
to find all configured instances.
Separate bug fix: Actually clear the MCPCIA error mask after probing for
PCI (and ISA) devices, don't just clear it twice in mcpcia_init0().
Some other slight cleanup.
the former, but not the latter. Hopefully, this will address some problems
people have been experiencing w/ some devices on Pyxis systems when BWX
is used for bus access. (If it's not used for PCI config access, we can
get fatal machine checks while probing behind PCI-PCI bridges!!)
before it can be useful, and [B] #ifdefs do not belong at every call site,
a common API should be defined and the implementations conditionalized, not
the calls. Duhh.
Also, remove the initial XXX mystery_icu debugging code.
Like the 1000A, the AlphaServer 1000 has a daughtercard assembly that
integrates the CPU and core logic, so these can be ev4/apecs or ev5/cia.
New systype, and, sigh, another way of doing interrupts and another
mystery icu.
Kill off some EVCNT_COUNTERS calls, since [A] it has to be rewritten anyway
before it can be useful, and [B] #ifdefs do not belong at every call site,
a common API should be defined and the implementations conditionalized, not
all the calls. Duhh.
AXPpci33 machines + power management and a Cirrus PCI-PCMCIA controller.
There is currently no support for the power management facilities, and
the PCI-PCMCIA controller driver needs some work, but this should boot
and run from disk.
the iot, memt, and pc in the call so that pci_1000a_pickintr() (and the
other routines in that module) do not need to be aware of the core logic
type just to pass down memory and I/O space tags or to call the decompose
function.
Use the check recommended by the Digital Workstation engineers; look
for Miata 1 systems (i.e. with Intel SIO). From Andrew Gallatin.
- Update copyright (Pyxis and BWX).
device 4. Miata 1.5 and Miata 2 have a Cypress at device 7 and PCI IDE
at functions 1 and 2 of the Cypress (like the PC164SX). These on-board
PCI IDE controllers are wired to compatibility mode, so don't bother
trying to map the interrupt.
on the ALCOR2 and Pyxis. BWX is enabled iff:
- It hasn't been disabled by the user (patch `cia_use_bwx' or build cia.o
with the option "CIA_USE_BWX=0"),
- it's enabled in CIA_CSR_CNFG,
- we are running on an EV5-family processor,
- BWX is in the processor's capabilities mask.
the scatter/gather TLB cannot be invalidated on these chips. So, to
work around this, we configure the otherwise unsed DMA Window 2 as a
2M SGMAP window at 128M, point all of its page table entries at the
DMA spill page, and, when the TLB is to be invalidated, put the PCI bus
into loopback mode, and create a target hit on Window 2 every 64k for
the number of TLB entries (plus a few ... it seems to not work unless
we read a few extra times), forcing out old TLB entries to make room for
the new, dummy target hits.
thorpej