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6cb1513d20
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723 Commits

Author SHA1 Message Date
christos
6cb1513d20 - fix an amd cache entry. 
- merge tables
- support phenom
from Paul Goyette
 2008-05-30 18:49:03 +00:00
christos
f26920b377 PR/38722: Paul Goyette: Share cacheinfo information 2008-05-30 14:42:42 +00:00
ad
0a34921e9f fillw is dead. 2008-05-30 11:03:29 +00:00
joerg
f608e44ab1 Add a function to extract the primary bus number of PCI host bridges, 
as far as specific code for this already existed.
 2008-05-30 09:49:07 +00:00
ad
0c8e56007e Remove X86_MAXPROCS. There is still a 32-cpu limit, but it's now using 
the MI constants.
 2008-05-28 11:50:01 +00:00
chs
736ec52d87 remove unused macros. 2008-05-25 16:01:29 +00:00
chris
2b534265d6 Check for erratum 261 on AMD Family 10h Stepping 3 processors. 
Also output any detected errata at verbose, rather than debug, level so
they can be seen with dmesg, and at least have a clue if a BIOS update
would fix the errata.
 2008-05-25 15:52:07 +00:00
chris
a868834e61 Add detection of errata for AMD Family 10h steppings A and 2. Covering 
errata:
254: Internal Resource Livelock Involving Cached TLB Reload
261: Processor May Stall Entering Stop-Grant Due to Pending Data
     Cache Scrub
298: L2 Eviction May Occur During Processor Operation To Set
     Accessed or Dirty Bit
309: Processor Core May Execute Incorrect Instructions on
     Concurrent L2 and Northbridge Response
 2008-05-25 15:19:22 +00:00
ad
d9b262b49d Mark x86_curlwp() with __attribute__ ((const)), so gcc can CSE it and know 
that it does not clobber global data.
 2008-05-22 13:55:51 +00:00
ad
b79cb03e74 Do the errata patchup after identifying the CPU, to avoid badly formatted 
output.
 2008-05-21 01:18:00 +00:00
ad
ca4aa34cf5 Be a bit less pointed with the errata warning. 2008-05-21 01:16:20 +00:00
ad
abeeffe66f aprint_debug for the lapic ESR reports during startup. 2008-05-21 01:15:16 +00:00
ad
e91baf0908 verbose -> debug for # page colours 2008-05-21 01:14:17 +00:00
ad
41fb29c26c cpuctl shows the power management features. 2008-05-21 01:13:07 +00:00
cegger
a8dd75a7ea correct comment copied from aiboost(4): envsys(4) wants uK 2008-05-20 14:45:22 +00:00
cegger
b112375268 envsys(4) expects values in mK and not the top of the range of possible temperature values. 
Needed some time to figure this out after I saw negative temperature values on Griffin.
 2008-05-20 13:58:32 +00:00
dogcow
49a3eaf487 due to changes in KERN_UNLOCK_ALL, now always define hold_count. 2008-05-20 09:29:33 +00:00
jmcneill
9709f2afe2 Add support for PCI_BUS_FIXUP and PCI_ADDR_FIXUP on amd64. 2008-05-18 02:06:14 +00:00
ad
bf1cf71fcd - cpu_attach: ensure that the boot processor is set up before trying to 
initialize APs. We need the lapic set up and the boot processor may
  not be attached first.

- mp_cpu_start: write back and invalidate the data cache before starting the
  init IPI sequence. If a buggy BIOS has left the AP with cache disabled,
  it might not be able to participate in the cache coherency protocol.
 2008-05-14 12:53:49 +00:00
ad
5d1d928fe1 Be more conservative during AP startup. Don't let the AP access the lapic 
or do any setup until the boot processor has finished the init sequence,
and add a few more delays.
 2008-05-13 22:39:17 +00:00
ad
62118300c8 intr_string: don't bother printing the legacy irq number when using the 
ioapic. It's confusing.
 2008-05-13 20:19:26 +00:00
joerg
816cef7d46 Restore the behaviour intended by rev 1.51 with the patch I actually 
send out for testing. The wrong version ended up in the commit.
Original description:
Don't use the legacy interrupt when deciding how to route IOAPIC pins.
On some modern systems not all devices have the PCI interrupt line
set, typically the cardbus bridge is affected and it would result in
different interrupt vectors used for the same IOAPIC pin.
To allow this, simplify the code by checking for an existing match first
and only allocate a new entry if that doesn't exist. For the IOAPIC case
don't bother with the reserveration on the primary CPU for ISA
interrupts, just use them.
 2008-05-13 14:29:17 +00:00
ad
5128f21c03 Back out 1.50 until the assumptions about NUM_LEGACY_IRQS are removed. 
Until then there are not enough free interrupt sources on UP systems.
(Sorry Joerg.)
 2008-05-13 12:14:06 +00:00
ad
25eae6f894 AMD and IDT/VIA strings were swapped. 2008-05-13 11:22:15 +00:00
ad
d3b40a28c7 - lapic_map: if we have an APIC MSR, ignore the supplied address and ask the 
hardware where it is mapped. At least one ACPI implementation seems to lie
  about the physical address of the lapic.

- lapic_initclocks: be paranoid and issue an EOI.
 2008-05-12 23:46:01 +00:00
ad
ce85d1b2a3 Some defs to describe the IA32_APIC_BASE MSR. 2008-05-12 18:36:20 +00:00
tsutsui
6f98953d90 Remove one more dup line. I should have a cup of coffee before hasty commit.. 
XXX maybe it's better to sort by cai_desc to sync with the Intel docs.
 2008-05-12 16:41:15 +00:00
ad
a1ba1eadd5 - Make cpu_number() return MI index, otherwise the pmap cannot work on 
systems with lapic IDs > X86_MAXPROCS.
- Kill cpu_info[] array and use MI cpu_lookup_byindex().
 2008-05-12 14:41:07 +00:00
ad
02ce2ed48b Don't crash if more than 32 cpus. Hopefully the boot processor will be 
within the first 32 attached.
 2008-05-12 14:29:06 +00:00
ad
453d5d4dc1 - Complain if unable to reset the lapic ID. 
- Minor clean up.
 2008-05-12 14:19:33 +00:00
ad
094788ba6d cpu_hatch: hack around problem with multiple CPUs spinning in i8254_delay. 2008-05-12 11:58:10 +00:00
simonb
ce7bd7383b Only need to add some of the new cache descriptors once(!). 2008-05-12 03:58:47 +00:00
cegger
79c3bfd61b remove one indent level. No functional change. 2008-05-11 23:05:45 +00:00
yamt
bf5accf9f6 tprof_backend_estimate_freq: ci_tsc_freq -> ci_data.cpu_cc_freq 2008-05-11 22:51:02 +00:00
ad
31c3804afc - Decouple the APIC ID from cpu_info[]. 
- Probe TSC frequency on each AP when hatching.
 2008-05-11 22:26:59 +00:00
ad
0dc71691a0 Fix the qemu (?) problem. 2008-05-11 22:18:08 +00:00
ad
fff73dae94 splclock -> splhigh 2008-05-11 21:50:06 +00:00
ad
704c817f7a Use ci_cpumask. 2008-05-11 21:48:02 +00:00
cegger
c094da181a print L3 and TLB cache information for AMD Barcelona/Phenom 2008-05-11 21:19:17 +00:00
tsutsui
f256c15ff3 Update intel_cpuid_cache_info as per Intel's application note: 
"AP-485 Intel(R) Processor Identification and the CPUID Instruction"
http://www.intel.com/design/processor/applnots/241618.htm

XXX1: should sort by cai_index or cai_desc?
XXX2: should also check L3CACHE for coloring?
 2008-05-11 18:29:42 +00:00
tsutsui
ce7c3e5d1c Fix an indent. 2008-05-11 18:21:28 +00:00
ad
a034c1c5e1 MP + apics are needed now so kill the #ifdefs 2008-05-11 16:26:56 +00:00
ad
b698c03c2c Don't reload LDTR unless a new value, which only happens for USER_LDT. 2008-05-11 16:23:05 +00:00
ad
5e605a64f7 Disable preemption across LDT mods. 2008-05-11 16:17:38 +00:00
ad
8250c8f097 Disable preemption over LDT modifications. 2008-05-11 16:13:34 +00:00
ad
3cd3c8ccbc Stop using APIC IDs to identify CPUs for software purposes. Allows for 
APIC IDs beyond 31, which has been possible for some time now.
 2008-05-11 15:59:50 +00:00
ad
f674d9678b Share cpu.h between the x86 ports. 2008-05-11 15:32:20 +00:00
ad
50d8ae9d14 Simplify x86 identcpu code, and share between i386/amd64. 2008-05-11 14:44:53 +00:00
ad
454ba0bbef Don't abuse ci_cpuid - in particular, ci_cpuid != ci_signature. 2008-05-11 14:39:49 +00:00
ad
f9a4f0750a Don't use ci_apicid to identify cpus in debug output. 2008-05-11 14:25:02 +00:00