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Add detection of errata for AMD Family 10h steppings A and 2. Covering

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errata:
254: Internal Resource Livelock Involving Cached TLB Reload
261: Processor May Stall Entering Stop-Grant Due to Pending Data
     Cache Scrub
298: L2 Eviction May Occur During Processor Operation To Set
     Accessed or Dirty Bit
309: Processor Core May Execute Incorrect Instructions on
     Concurrent L2 and Northbridge Response
This commit is contained in:
chris 2008-05-25 15:19:22 +00:00
parent 1e2888bbbd
commit a868834e61
2 changed files with 49 additions and 3 deletions
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7
sys/arch/x86/include/specialreg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: specialreg.h,v 1.23 2008/02/03 06:19:06 xtraeme Exp $ */
/* $NetBSD: specialreg.h,v 1.24 2008/05/25 15:19:22 chris Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@ -354,6 +354,7 @@
* These require a 'passcode' for access. See cpufunc.h.
*/
#define MSR_HWCR 0xc0010015
#define HWCR_TLBCACHEDIS 0x00000008
#define HWCR_FFDIS 0x00000040
#define MSR_NB_CFG 0xc001001f
@ -369,8 +370,12 @@
#define MSR_DC_CFG 0xc0011022
#define DC_CFG_DIS_CNV_WC_SSO 0x00000004
#define DC_CFG_DIS_SMC_CHK_BUF 0x00000400
#define DC_CFG_ERRATA_261 0x01000000
#define MSR_BU_CFG 0xc0011023
#define BU_CFG_ERRATA_298 0x0000000000000002ULL
#define BU_CFG_ERRATA_254 0x0000000000200000ULL
#define BU_CFG_ERRATA_309 0x0000000000800000ULL
#define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL
#define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL
#define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL

45
sys/arch/x86/x86/errata.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: errata.c,v 1.16 2008/05/21 01:16:20 ad Exp $ */
/* $NetBSD: errata.c,v 1.17 2008/05/25 15:19:22 chris Exp $ */
/*-
* Copyright (c) 2007 The NetBSD Foundation, Inc.
@ -45,7 +45,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: errata.c,v 1.16 2008/05/21 01:16:20 ad Exp $");
__KERNEL_RCSID(0, "$NetBSD: errata.c,v 1.17 2008/05/25 15:19:22 chris Exp $");
#include <sys/types.h>
#include <sys/systm.h>
@ -69,6 +69,7 @@ typedef struct errata {
typedef enum cpurev {
BH_E4, CH_CG, CH_D0, DH_CG, DH_D0, DH_E3, DH_E6, JH_E1,
JH_E6, SH_B0, SH_B3, SH_C0, SH_CG, SH_D0, SH_E4, SH_E5,
DR_BA, DR_B2,
OINK
} cpurev_t;
@ -83,6 +84,7 @@ static const u_int cpurevs[] = {
SH_CG, 0x0000f4a, SH_CG, 0x0000f5a, SH_CG, 0x0000f7a,
SH_D0, 0x0010f40, SH_D0, 0x0010f50, SH_D0, 0x0010f70,
SH_E4, 0x0020f51, SH_E4, 0x0020f71, SH_E5, 0x0020f42,
DR_BA, 0x0100f2a, DR_B2, 0x0100f22,
OINK
};
@ -122,6 +124,10 @@ static const uint8_t x86_errata_set8[] = {
SH_D0, SH_D0, SH_D0, SH_E4, SH_E4, SH_E5, OINK
};
static const uint8_t x86_errata_set9[] = {
DR_BA, DR_B2, OINK
};
static bool x86_errata_setmsr(struct cpu_info *, errata_t *);
static bool x86_errata_testmsr(struct cpu_info *, errata_t *);
@ -223,6 +229,41 @@ static errata_t errata[] = {
122, FALSE, MSR_HWCR, x86_errata_set4,
x86_errata_setmsr, HWCR_FFDIS
},
/*
* 254: Internal Resource Livelock Involving Cached TLB Reload
*/
{
254, FALSE, MSR_BU_CFG, x86_errata_set9,
x86_errata_testmsr, BU_CFG_ERRATA_254
},
/*
* 261: Processor May Stall Entering Stop-Grant Due to Pending Data
* Cache Scrub
*/
{
261, FALSE, MSR_DC_CFG, x86_errata_set9,
x86_errata_testmsr, DC_CFG_ERRATA_261
},
/*
* 298: L2 Eviction May Occur During Processor Operation To Set
* Accessed or Dirty Bit
*/
{
298, FALSE, MSR_HWCR, x86_errata_set9,
x86_errata_testmsr, HWCR_TLBCACHEDIS
},
{
298, FALSE, MSR_BU_CFG, x86_errata_set9,
x86_errata_testmsr, BU_CFG_ERRATA_298
},
/*
* 309: Processor Core May Execute Incorrect Instructions on
* Concurrent L2 and Northbridge Response
*/
{
309, FALSE, MSR_BU_CFG, x86_errata_set9,
x86_errata_testmsr, BU_CFG_ERRATA_309
},
};
static bool