On some modern systems not all devices have the PCI interrupt line
set, typically the cardbus bridge is affected and it would result in
different interrupt vectors used for the same IOAPIC pin.
To allow this, simplify the code by checking for an existing match first
and only allocate a new entry if that doesn't exist. For the IOAPIC case
don't bother with the reserveration on the primary CPU for ISA
interrupts, just use them.
- Ditch the cross-CPU calibration stuff. It didn't work properly, and it's
near impossible to synchronize the CPUs in a running system, because bus
traffic will interfere with any calibration attempt, messing up the
timings.
- Only enable the TSC on CPUs where we are sure it does not drift. If we are
On a known good CPU, give the TSC high timecounter quality, making it the
default.
- When booting CPUs, detect TSC skew and account for it. Most Intel MP
systems have synchronized counters, but that need not be true if the
system has a complicated bus structure. As far as I know, AMD systems
do not have synchronized TSCs and so we need to handle skew.
- While an AP is waiting to be set running, try and make the TSC drift by
entering a reduced power state. If we detect drift, ensure that the TSC
does not get a high timecounter quality. This should not happen and is
only for safety.
- Make cpu_counter() stuff LKM safe.
Select the Xen idle routine for Xen, mwait if supported by the CPU and
it is not AMD and halt otherwise. As reported by Christoph Egger,
AMD Barcelona keeps the CPU in C0 state with MWAIT, contrary to HLT,
which uses C1 and therefore much less power.
into the kernel. Based on a patch by jmcneill@, with many fixes and
improvements by me.
- Put MEMORY_DISK_DYNAMIC and MODULAR into the GENERIC kernels, so that
you can load miniroot.kmod from the boot blocks and boot into the
installer!
- I have seen one isolated panic in the x86 pmap, but otherwise i386
seems stable with preemption enabled.
- amd64 is missing the FPU handling changes and it's not yet safe to
enable it there.
- The usual level for kern.sched.kpreempt_pri will be 128 once enabled
by default. For testing, setting it to 0 helps to shake out bugs.
DragonflyBSD uses the crit names for something quite different.
- Add a kpreempt_disabled function for diagnostic assertions.
- Add inline versions of kpreempt_enable/kpreempt_disable for primitives.
- Make some more changes for preemption safety to the x86 pmap.
Changes beyond OpenBSD's driver:
- Improved support for AMD K8
- Added support for AMD Barcelona, AMD Phenom and AMD Griffin
Tested on various single and multi-socket machines.
Review and OK xtreame
pointed out by Simon (Simon's option #3): use the greatest power of two
which is a divisor of the desired number of cache colors.
This code might want to stay even after the cache probing code is fixed.
usable VGA console ("call ddb_vgapost")
-allow to switch from/to screens occupied by an X server if the graphics
device is console and in polling mode (ie DDB)
This together allows to get a DDB session on a VGA console if the
system crashed while X11 was running.
As long as the protocol to tell X servers about virtual screen switches
is as primitive as it is, it is unsafe to restart an X session afterwards.
So this is basically for crash analysis.
polling the i8254 as reference and counting the cycles with that.
Disable interrupts. This should be relatively stable even in the light
of SMIs as long as they happen in the middle of the loop. This fixes
long delays during boot.
If greater precision for the calibration is desired, a second run should
be done at a different time when the HPET or ACPI timer is present. Both
provide much faster access (less jitter) and a higher frequency.
