- Move away from using CPUISMIPS3; use MIPS_HAS_R4K_MMU instead.
- Bump the Sysmap size a little for large-memory machines.
XXX: still need work, especially in pmap_procwr().
- Use a table-driven CPU detection algorithm instead of multiple
case statements.
- Add MIPS32/64 feature detection using the architected CP0 registers
(from Broadcom Corp).
- Call MD mips_machdep_cache_config() function if
__HAVE_MIPS_MACHDEP_CACHE_CONFIG is defined - used to set up the
L2 cache on some ports.
- Remove all mmu-related code that may use 32 register on mips32-style
implementatios and move them to mipsX_subr.S - which is then included
from mips{3,32,64,5900}_subr.S with various control defines enabled.
- Remove local cache instruction flags
- Add badaddr64 (from Broadcom Corp).
- Add mips32 and mips64 locore function prototypes.
- Add mips3_lw_a64() and mips3_sw_a64() for access data at any
64bit address (from Broadcom Corp).
- Add Broadcom and Sandcraft CPU company ids.
- Add XKPHYS macros (from Broadcom Corp).
- Add some r5900 register bit definitions.
- Add extra exception vector addresses for mips32/mips64 and r5900.
- Make the mips cp0 register definitions available from both asm and C.
- Add some Alchemy and Sandcraft CPU ids.
- Add r3000, tx39xx and r4x00 CPU revision ids.
- Remove defines for the number of TLBs on some CPUs.
- Add alignment-safe double and float unions.
- Use the above for the __infinity and __nan constants on all
architectures that use the standard ieee754 representation of
those constants.
- Add a single copy of various ieee754 math functions (frexp, isinf,
isnan, ldexp and modf) that had numerous duplicates among the
arch-specific directories.
- Use the above functions on all architectures where the generic C
versions where used. Architectures that had local assembly
routines are untouched (for those functions only).
Any problems reported by testers have been fixed, and massive
cross-compiling of kernels has shown that any problems that remain
with actually building kernels are not related to this.
not support a value (e.g., it's to be used as "options FOO" instead of
"options FOO=xxx"). options that take a value were converted to
defparam recently.
- minor whitespace & formatting cleanups
contain information suitable for allowing other parts of the kernel
to determine if a memory region is aligned to the largest data cache
line size present in the system.
Add a mips_dcache_compute_align() function which must be called whenever
one of the data cache line size variables is changed, in order to
compute mips_dcache_align and mips_dcache_align_mask.
executable mappings. Stop overloading VTEXT for this purpose (VTEXT
also has another meaning).
- Rename vn_marktext() to vn_markexec(), and use it when executable
mappings of a vnode are established.
- In places where we want to set VTEXT, set it in v_flag directly, rather
than making a function call to do this (it no longer makes sense to
use a function call, since we no longer overload VTEXT with VEXECMAP's
meaning).
VEXECMAP suggested by Chuq Silvers.
the etc Makefile override that by putting USETOOLS into $.MAKEOVERRIDES
This way the default for kernel compiles is still to use the installed
toolchain instead of depending on $TOOLDIR. $TOOLDIR can be used by
simply adding USETOOLS=yes to the command line as usual.
Adjust each ports template to set the default no setting and also pull in
bsd.own.mk if they weren't already to ensure they'll build correctly
with the new toolchain setup.
COP0_SYNC
In R5900 mtc0, tlbr, tlbp, tlbwi, tlbwr must be followed by sync.p.
if defined MIPS3_5900, COP0_SYNC is defined as sync.p. else nothing.
IPL_ICU_MASK
mask interrupt directly ICU instead of SR.IM.
I've added this feature to support software interrupt for R5900.
and this option may be useful for platform which has cascaded ICU.
kernel compile flags as well as "-mlong-calls" so that calls from the
LKM in KSEG2 work to the kernel in KSEG0.
MIPS LKMs now build and can be loaded with the right Magick command line
args to modload(8). Changes to modload coming...
Thanks to Chris Demetriou for pointing out the -mlong-calls gcc option
that had been staring me in the face all along.
use command line parameters to ld(1) instead to set the endian format.
Clean up some endian decisions in mips/conf/Makefile.mips.
Wrap some long lines.
format specific.
Struct emul has a e_setregs hook back, which points to emulation-specific
setregs function. es_setregs of struct execsw now only points to
optional executable-specific setup function (this is only used for
ECOFF).
This will allow improvements to the pmaps so that they can more easily defer expensive operations, eg tlb/cache flush, til the last possible moment.
Currently this is a no-op on most platforms, so they should see no difference.
Reviewed by Jason.
need to check for curproc being non-NULL since none of the pmap
interfaces which are legal to use in interrupt handlers use this macro.
- use the hit op when flushing the cache in pmap_kremove().
- avoid trusting the optimizer in pmap_clear_reference().
- fix pmap_clear_modify() to reset the mod-bit emulation so we can
detect further modifications to the page, also flushing the cache
for any mappings which might have dirty lines.
passed which is larger than an int but has int alignment. As well as
fixing the described problem, this is the same way it is handled in the
Irix and Ultrix header files.
Problem and suggested solution by Uros Prestor in port-mips mailling
list.
remove some checks for impossible conditions.
in pmap_enter(), only call pmap_remove() to remove an existing mapping
if there actually is an existing mapping.
in pmap_remove_pv(), don't flush the MIPS1 cache when removing the last mapping.
this was added in rev 1.97, to avoid stale data being left in the cache
when the page is zeroed bypassing the cache in pmap_zero_page_uncached().
we've since found that bypassing the cache for idle-loop page zeroing
doesn't work very well anyway, so we don't do that anymore.
so now we can remove the extra cache-flush.
remove pmap_zero_page_uncached() while I'm thinking of it.
various other cleanup.
interrupt to sneak in after EXL had been set; the interrupt EPC was stale
as PC isn't saved if EXL is set, causing the eret to return to the wrong
place and leading to kernel-mode TLB misses on user addresses. The bug
was discovered by the japanese NetBSD/*mips folks and the same fix was
found independently by shinohara-san (shin@netbsd.org).
- Use pools for pmap structures and pv_entry structures.
- Remove a bunch of splvm()/splx(), no longer needed now that
pmap_kenter_pa() and pmap_kremove() are as they should be.
Mostly from Chuck Silvers.
there are just far too many combinations to handle with magic
#ifdefs in any sane way. Also, add a HitFlushDCache op to the
"locoresw", and fill it in as appropriate (it's NULL on MIPS-I,
so watch out).
These changes ensure that my R4600 Indy (with 2-way cache) gets
the correct cache ops when the kernel is built with only MIPS3
support, resulting in a kernel that is significantly more stable.
distinguished by SYSID register in the system controller. Note
that PRiD 0x20 is for a standalone RC32364 processor which has the
same 32300 core inside. Rather better to name them MIPS32 ISA.
