ANSIfy, KNF.
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0667ea6c1c
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@ -1,4 +1,4 @@
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/* $NetBSD: db_interface.c,v 1.36 2001/05/30 15:24:33 lukem Exp $ */
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/* $NetBSD: db_interface.c,v 1.37 2001/08/27 06:18:08 simonb Exp $ */
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/*
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* Mach Operating System
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@ -58,38 +58,40 @@
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int db_active = 0;
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mips_reg_t kdbaux[11]; /* XXX struct switchframe: better inside curpcb? XXX */
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void db_tlbdump_cmd __P((db_expr_t, int, db_expr_t, char *));
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void db_kvtophys_cmd __P((db_expr_t, int, db_expr_t, char *));
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void db_tlbdump_cmd(db_expr_t, int, db_expr_t, char *);
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void db_kvtophys_cmd(db_expr_t, int, db_expr_t, char *);
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static void kdbpoke_4 __P((vaddr_t addr, int newval));
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static void kdbpoke_2 __P((vaddr_t addr, short newval));
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static void kdbpoke_1 __P((vaddr_t addr, char newval));
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static short kdbpeek_2 __P((vaddr_t addr));
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static char kdbpeek_1 __P((vaddr_t addr));
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extern vaddr_t MachEmulateBranch __P((struct frame *, vaddr_t, unsigned, int));
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static void kdbpoke_4(vaddr_t addr, int newval);
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static void kdbpoke_2(vaddr_t addr, short newval);
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static void kdbpoke_1(vaddr_t addr, char newval);
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static short kdbpeek_2(vaddr_t addr);
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static char kdbpeek_1(vaddr_t addr);
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extern vaddr_t MachEmulateBranch(struct frame *, vaddr_t, unsigned, int);
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extern paddr_t kvtophys __P((vaddr_t));
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extern paddr_t kvtophys(vaddr_t);
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#ifdef DDB_TRACE
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int
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kdbpeek(addr)
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vaddr_t addr;
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kdbpeek(vaddr_t addr)
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{
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if (addr == 0 || (addr & 3))
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return 0;
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return *(int *)addr;
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}
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#endif
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static short
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kdbpeek_2(addr)
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vaddr_t addr;
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kdbpeek_2(vaddr_t addr)
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{
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return *(short *)addr;
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}
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static char
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kdbpeek_1(addr)
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vaddr_t addr;
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kdbpeek_1(vaddr_t addr)
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{
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return *(char *)addr;
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}
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@ -101,6 +103,7 @@ kdbpeek_1(addr)
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static void
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kdbpoke_4(vaddr_t addr, int newval)
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{
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*(int*) addr = newval;
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wbflush();
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}
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@ -108,6 +111,7 @@ kdbpoke_4(vaddr_t addr, int newval)
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static void
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kdbpoke_2(vaddr_t addr, short newval)
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{
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*(short*) addr = newval;
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wbflush();
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}
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@ -124,9 +128,9 @@ kdbpoke_1(vaddr_t addr, char newval)
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* Received keyboard interrupt sequence.
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*/
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void
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kdb_kbd_trap(tf)
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int *tf;
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kdb_kbd_trap(int *tf)
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{
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if (db_active == 0 && (boothowto & RB_KDB)) {
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printf("\n\nkernel: keyboard interrupt\n");
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ddb_trap(-1, tf);
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@ -136,10 +140,9 @@ kdb_kbd_trap(tf)
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#ifndef KGDB
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int
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kdb_trap(type, tfp)
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int type;
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mips_reg_t *tfp; /* struct trapframe */
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kdb_trap(int type, mips_reg_t /* struct trapframe */ *tfp)
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{
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struct frame *f = (struct frame *)&ddb_regs;
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#ifdef notyet
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@ -208,16 +211,15 @@ kdb_trap(type, tfp)
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}
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void
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cpu_Debugger()
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cpu_Debugger(void)
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{
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asm("break");
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}
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#endif /* !KGDB */
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void
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db_set_ddb_regs(type, tfp)
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int type;
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mips_reg_t *tfp;
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db_set_ddb_regs(int type, mips_reg_t *tfp)
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{
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struct frame *f = (struct frame *)&ddb_regs;
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@ -267,11 +269,9 @@ db_set_ddb_regs(type, tfp)
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* Read bytes from kernel address space for debugger.
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*/
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void
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db_read_bytes(addr, size, data)
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vaddr_t addr;
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size_t size;
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char *data;
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db_read_bytes(vaddr_t addr, size_t size, char *data)
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{
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while (size >= 4)
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*((int*)data)++ = kdbpeek(addr), addr += 4, size -= 4;
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while (size >= 2)
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* Write bytes to kernel address space for debugger.
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*/
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void
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db_write_bytes(addr, size, data)
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vaddr_t addr;
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size_t size;
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char *data;
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db_write_bytes(vaddr_t addr, size_t size, char *data)
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{
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vaddr_t p = addr;
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size_t n = size;
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#ifdef DEBUG_DDB
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printf("db_write_bytes(%lx, %d, %p, val %x)\n", addr, size, data,
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(addr &3 ) == 0? *(u_int*)addr: -1);
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#ifndef KGDB
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void
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db_tlbdump_cmd(addr, have_addr, count, modif)
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db_expr_t addr;
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int have_addr;
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db_expr_t count;
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char *modif;
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db_tlbdump_cmd(db_expr_t addr, int have_addr, db_expr_t count, char *modif)
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{
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#ifdef MIPS1
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if (!CPUISMIPS3) {
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struct mips1_tlb {
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u_int32_t tlb_lo;
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} tlb;
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int i;
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void mips1_TLBRead __P((int, struct mips1_tlb *));
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void mips1_TLBRead(int, struct mips1_tlb *);
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for (i = 0; i < mips_num_tlb_entries; i++) {
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mips1_TLBRead(i, &tlb);
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}
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void
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db_kvtophys_cmd(addr, have_addr, count, modif)
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db_expr_t addr;
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int have_addr;
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db_expr_t count;
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char *modif;
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db_kvtophys_cmd(db_expr_t addr, int have_addr, db_expr_t count, char *modif)
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{
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if (!have_addr)
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return;
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if (MIPS_KSEG2_START <= addr) {
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{ "tlb", db_tlbdump_cmd, 0, 0 },
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{ (char *)0, }
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};
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#endif /* !KGDB */
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/*
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* Determine whether the instruction involves a delay slot.
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*/
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boolean_t
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inst_branch(inst)
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int inst;
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inst_branch(int inst)
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{
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InstFmt i;
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int delay;
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* Determine whether the instruction calls a function.
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*/
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boolean_t
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inst_call(inst)
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int inst;
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inst_call(int inst)
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{
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boolean_t call;
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InstFmt i;
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* This lets the ddb "next" command to work (also need inst_trap_return()).
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*/
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boolean_t
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inst_return(inst)
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int inst;
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inst_return(int inst)
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{
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InstFmt i;
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* Determine whether the instruction makes a jump.
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*/
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boolean_t
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inst_unconditional_flow_transfer(inst)
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int inst;
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inst_unconditional_flow_transfer(int inst)
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{
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InstFmt i;
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boolean_t jump;
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* Determine whether the instruction is a load/store as appropriate.
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*/
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boolean_t
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inst_load(inst)
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int inst;
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inst_load(int inst)
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{
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InstFmt i;
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}
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boolean_t
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inst_store(inst)
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int inst;
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inst_store(int inst)
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{
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InstFmt i;
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* MachEmulateBranch() runs analysis for branch delay slot.
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*/
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db_addr_t
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branch_taken(inst, pc, regs)
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int inst;
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db_addr_t pc;
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db_regs_t *regs;
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branch_taken(int inst, db_addr_t pc, db_regs_t *regs)
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{
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vaddr_t ra;
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unsigned fpucsr;
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* Return the next pc of an arbitrary instruction.
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*/
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db_addr_t
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next_instr_address(pc, bd)
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db_addr_t pc;
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boolean_t bd;
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next_instr_address(db_addr_t pc, boolean_t bd)
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{
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unsigned ins;
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