- Change structures for each device to make them more suitable with
our scsipi mid-layer.
- Use ADAPTER_REQ_SET_XFER_MODE callback.
- Cleanup misc functions/structures/style.
XXX Tagged queuieng support is disabled for now.
XXX Maybe we should have common library of the scsi protocol engine
XXX to share it among all other drivers..
sequence using the reciprocal of the delay divisor to perform the
division.
Set the cp0 compare register so that it doesn't trigger interrupts and
reset the cp0 count register in the hardclock interrupt handler.
To implement a more accurate microtime using the CP0 COUNT
register we need to divide that register by the number of
cycles per MHz. But...
DIV and DIVU are expensive on MIPS (eg 75 clocks on the
R4000). MULT and MULTU are only 12 clocks on the same CPU.
On the SB1 these appear to be 40-72 clocks for DIV/DIVU and 3
clocks for MUL/MULTU.
The strategy we use to to calculate the reciprical of cycles
per MHz, scaled by 1<<32. Then we can simply issue a MULTU
and pluck of the HI register and have the results of the
division.
"swarm"). Other SB-cpu boards will be supported by this port in
the future.
Includes support for on-chip ethernet and serial. Many features
still missing - notably SMP, PCI/LDT and IDE.
This code is provided by the Broadband Processor Business Unit at
Broadcom Corp with minor updates by me.
and support routines for the Broadcom CFE (Common Firmware Environment).
This code is provided by the Broadband Processor Business Unit at
Broadcom Corp with minor updates by me.
- Move away from using CPUISMIPS3; use MIPS_HAS_R4K_MMU instead.
- Bump the Sysmap size a little for large-memory machines.
XXX: still need work, especially in pmap_procwr().
- Use a table-driven CPU detection algorithm instead of multiple
case statements.
- Add MIPS32/64 feature detection using the architected CP0 registers
(from Broadcom Corp).
- Call MD mips_machdep_cache_config() function if
__HAVE_MIPS_MACHDEP_CACHE_CONFIG is defined - used to set up the
L2 cache on some ports.
- Remove all mmu-related code that may use 32 register on mips32-style
implementatios and move them to mipsX_subr.S - which is then included
from mips{3,32,64,5900}_subr.S with various control defines enabled.
- Remove local cache instruction flags
- Add badaddr64 (from Broadcom Corp).
tsutsui