* Add the correct version of locore_mips1.S [ See previous revision for
description of changes ]
* Use defopt'ed MIPS3_L2CACHE_ABSENT in mips_machdep.c and pmap.c
to avoid generating extraneous code.
* GC pmap_set_referenced in pmap.c
minor of libc and the major of libutil). For little-endian architectures
merge the bnswap() assembly versions with nto* and hton* using symbols
aliasing. Use symbol renaming for the bswap function in this case to avoid
namespace pollution.
Declare bswap* in machine/bswap.h, not machine/endian.h. For little-endian
machines, common code for inline macros go in machine/byte_swap.h
Sync libkern with libc.
Adjust #include in kernel sources for machine/bswap.h.
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.
* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.
* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.
* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors
UVM relies on pmap modules keeping track of modified/referenced bits
after a page has been removed from all mappings. So *dont* clear
PV_REFERENCED or PV_MODIFIED flags in pmap_remove().
Track page modification status in the PV entry like the alpha, and let
pmap_is_modified() return current status back to the VM system. UVM now
works reliably.
Garbage collect the old pmap_attribute[] stuff.
- cpu_set_kpc() now takes void *arg third argument, passed to the
entry point.
- cpu_fork() allows parent to be non-curproc iff parent is proc0.
When forking non-curproc, assume its state has already been saved.
- Adjust various pieces of machine-dependent code to account of all of this.
* commit isapnpvar.h changes required for ARC to support plain isa.
* fixup mistake over mips/include/cpuregs.h.
* mips/mips_machdep.c:
set L2 cache-size for arc, cleanup use of L2cache present
vs L2 cache-size variables. check for no L2 cache on kernels
configured to require one. misc cleanups.
* mips/mpis/trap.c: more locore stack-traceback label cleanup.
XXX Locore callbacks for mips3, mips4, r4600 cacheflush need more work.
Adds (most) support for ARC platform to port-independent mips code.
Some changes (e.g., clean up of overlapping CPU/FPU ids) inspired by
comparison to the OpenBSD 2.1 codebase of Soda's ARC port.
Open issues:
* Still no support for r4600 or mipsIV CPUs with two-way L1 cache.
Code derived from Per Fogelstrom's OpenBSD source doesn't work
on mips3 pmaxes with L2 cache.
* Still some port-specific #ifdefs, for interrupt enable and
pmax L2 cache-size. Needs more thought, but overlaps with
work-in-progress by Tohru and Tsubai on spl()s and related stuff.
nisimura