cacheable attribute of a mapping.
- Honour PMAP_NC in pmap_enter() using NOCACHE, instead of DEVICE.
- No longer need to re-fetch the ptel in pmap_pa_unmap_kva() as
syncing the cache no longer risks causing a TLB miss.
- Re-define bus_size_t and bus_addr_t to be u_int32_t.
While this may well lose for future silicon with NEFFBITS > 32, the
original u_long was a waste on current designs (especially for _LP64).
registers in any trap/interrupt exception frame found.
- Slight tweak to more accurately detect the correct call-site when
looking for a function's prologue.
problem, such that a TLB miss no longer occurs.
With the above, it is now safe to enable write-back caching for userland
mappings.
TODO: Deal with cache issues for shared mappings with different VAs.
- Add event counters for some key pmap events (similar to mpc6xx pmap).
- Use the cache-friendly, optimised copy/zero page functions.
- Add the necessary cache management code to enable WriteBack caching
of KSEG1 mappings. Seems to work fine so far.
section of another exception. This is likely to happen if the kernel
stack is misaligned, has dropped off the bottom of the PCB, or has
otherwise gone into orbit.
In this case, switch to a safe stack, save as much of the machine
state as possible and dump it to the console.
as intrframe and trapframe are concerned.
According to the ABI, only the low 32-bits of these registers are
guaranteed to be preserved by the callee. Therefore, we need to
preserve all 64-bits of them in the interrupt trampoline.
At the very least, this will dump the machine state. At best,
we get into ddb().
This provides a useful way to regain control using an NMI button
if the cpu decides to spin at a high ipl.
previous behaviour of storing them with SR.BL clear was in breach
of the SH5 documentation.
Make an effort to catch PANIC traps and dump machine state to the console.
pcb contains valid state before copying it to p2's pcb.
Previously, we just lazy-sync the fpu state. This wasn't quite good
enough if p1 had not previously slept.
counters. These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.
pmc(9) is meant to be a general interface. Initially, the Intel XScale
counters are the only ones supported.
simple config file option.
Also, don't hard code the endian setting in a header file. Rely instead
on the compiler defining __LITTLE_ENDIAN__ and DTRT as appropriate.
