Commit Graph

325 Commits

Author SHA1 Message Date
mhitch b4af013102 Resident count in pmap is now valid. I can now see RSS in ps. 1997-07-29 01:43:26 +00:00
mhitch fd5f2fd062 Get rid of the MIPS3 mess I left in pmap_enter_pv(). The cache inhibit
of cache-index incompatible virtual mappings for a physical page may be
required for hardware without secondary (level 2) cache to detect and
correct virtual coherency problems.  I'm not sure this is really needed
anymore, since pmap_prefer() took care of of the cache-index
incompatible mappings that I have seen.  Count the times a page is
cache inhibited in enter_stats if DEBUG.

Wait for memory instead of panic() on failure to allocate a page for the
segtab or segmap [from OpenBSD arc port].  Also check for malloc()
failure on allocation of a new pv entry and panic().

Increment resident_count when adding a new page to a pmap [also from
OpenBSD].  Process resident size is now valid.
1997-07-29 01:41:46 +00:00
jonathan 98d9a419f8 Add comments to pmap_copy_page() and pmap_zero_page() describing the
cache flush operations required on a virtually-indexed, physically-tagged
mips3 with no L2 cache to provide cache-coherence exceptions.

(Similar to what's needed with a virtually-indexed, virtually-tagged cache.)
1997-07-28 20:41:58 +00:00
mhitch 8e145a319b Don't rely on curproc to access the current pcb when testing for kernel
faults.  Use curpcb, which always points to the current pcb.  If curproc
was NULL when the kernel faulted, the trap handling would fault recursively
and the kernel stack would overflow.
1997-07-26 19:46:40 +00:00
jonathan f9e3ce0f92 revert to MI in_cksum code. 1997-07-25 21:01:45 +00:00
jonathan 83ebfc3545 Unroll pmap_copy_page() and pmap_zero_page() inlined loops even further. 1997-07-23 05:41:17 +00:00
jonathan b1032ac9db Substitute Mach 3.0 MK84 mips kernel bcopy() for Sprite bcopy().
Has unrolled loop for aligned-to-aligned copy.

Notes:
  1. this code tuned for DEC 5000/200.  ioasic decstations do more unaligned
     copies.  Better than old non-unrolled loop, but could be improved.

  2. Undoes changes made for MIPS3 with comment implying an r4000 TLB bug.
     We can't reproduce this on 5000/150 (jonathan) or 5000/50 (mhitch).
     Calls to previous  bcopy with a bad address show similar symptoms,
     reporting a trap in bcopy() after bcopy() has returned.  Same thing??
     Needs re-checking on an r4000 with no L2 cache.
1997-07-23 05:36:40 +00:00
jonathan a6c118666a Fix for chains containing interior mbufs with odd length. 1997-07-22 07:36:18 +00:00
jonathan 592eeb7378 mips-tuned bcopy from Jon Kay (UCSD) released under BSD copyright,
with standard BSD in_cksum() interface by Jonathan Stone.
1997-07-20 22:42:33 +00:00
jonathan f43c13bff4 Add ddb to mips/conf/files.mips. Garbage-collect mdb. 1997-07-20 20:48:40 +00:00
jonathan 5ba85a4cf8 Kernel profiling. Don't profile the following:
sigcode():
      executed from user-space stack.

  mips1_cpu_switch_resume, mips3_cpu_switch_resume:
      arguments passed in via v0, t0, t1 (outlined from cpu_switch())

  mips3_VCED(), mips3_VCEI():
      called from exception-vector code without any register save,
      $at, $ra are live.
1997-07-20 19:48:03 +00:00
jonathan 01794f87e3 Conditionalize mips1-speciifc locore code on #ifdef MIPS1 1997-07-20 19:40:19 +00:00
jonathan fd7a6758c8 Don't emit ".set reorder ; .set noreorder" around mcount profiling
stubs if _LOCORE or _KERNEL are defined,.  _LOCORE means we're
compiling locore. Locore assumes ".set noreorder" for the whole file.
1997-07-20 09:47:03 +00:00
jonathan 9f89c0da89 Use __attribute__((unused). From Chris G. Demetriou <cgd@pa.dec.com>. 1997-07-20 03:47:29 +00:00
jonathan caea1075c9 * Do staktcraces back through traps from kernel mode.
* Don't take  stack adjustment inside procedures as frame size
  (e.g.,  8-byte stack adjustment for calling _mcount).
1997-07-20 03:46:20 +00:00
jonathan 06df97095c Add ecoff ``struct ext_ext'' header fields to ecoff_extsym.h.
Compatible with mips ECOFF nm from GNu binutils or MipsCo toolchain.
1997-07-20 02:38:02 +00:00
jonathan 39814d8abc Add pointer to _mcount to avoid bogus warnings about unused static function.
(calls from interpolated assembler are invisible to gcc.)

If _KERNEL, add prototypes for non-profiled entrypoints _splhigh(), _splx().
1997-07-19 21:30:25 +00:00
jonathan ccf3801c92 * Re-apply changes from rev 1.6 of sys/arch/mips/include/reg.h accidentally
undone by rev 1.7:
  >redo pmax/include/reg.h
  >so that the definitions needed by locore.S are in a separate file,
  >pmax/include/regnum.h.

* Add explicit `#include <mips/regnum.h>'  where symbolic offsets
  into a mips trapframe or struct reg are used..
1997-07-19 09:54:23 +00:00
perry ad1710ce1e update comment from 1981 on memory and disk prices -- pr-2754 from Curt Sampson 1997-07-12 16:18:36 +00:00
jonathan 1490cbcf7b Rewrite struct ecoff_symhdr using the same field ordering as GNU
binutils and the MipsCo toolchain, not the Alpha ordering (which has a
block of int32_t symbol counts and a block of long offsets) .
1997-07-07 19:37:33 +00:00
jonathan 65e2c70353 Force write-back of D-cache after doing DDB writes on mips3. Flushing
the Icache is not sufficient: a mips3 can write a new insn into
writeback L1 Dcache, leaving stale instructions in the mixed L2 cache.
1997-07-07 04:55:27 +00:00
jonathan 919bc0ce92 Typo in RCS id. 1997-07-07 03:57:55 +00:00
jonathan d1ec048977 DDB for mips.
Add DDB interface to /sys/arch/mips/mips..
  Rework heuristic stack traceback to work with DDB.
  Add hooks  to print exception log from DDB.
  Add hooks from pmax console drivers:   call Debugger()
  after break from serial console, or 'DO' key from LK-xxx.
1997-07-07 03:54:24 +00:00
jonathan da53d70f23 Move generic mips functions setregs(), sendsig(), sys_signal()
to sys/arch/mips/mips/mips_machdep.c.  Delete from pica, pmax machdep.c.

Delint pica machdep.c.
1997-07-01 09:32:13 +00:00
jonathan 8586e62e14 Enable stack tracebacks if MDB is configured. 1997-06-30 14:42:32 +00:00
mhitch d6b6efec34 Moved the mini-debug routines out of trap.c into their own file, like the
original pica port.
1997-06-28 03:59:46 +00:00
mhitch a503f4436c Mini-debuuger is now included by options MDB.
Move mini-debugger routines to separate file, minidebug.c.
1997-06-28 03:57:55 +00:00
mhitch 566b174c13 Mini-debugger now included by options MDB.
Cpu_regs() is included by options DEBUG, as are the stacktrace routines,
so move it inside the #ifdef DEBUG along with stacktrace().
1997-06-28 03:55:05 +00:00
mhitch 8c12914cdb Fix typo.
Include minidebug.c with options MDB.
1997-06-28 03:43:21 +00:00
mhitch 63f2f12797 Someday I'll learn how the MIPS cpu works; add some delay after the tlbp
when switching to a new process.  This was causing a ktlbmiss and stack
overflow panic on R3000 machines.
1997-06-25 05:06:01 +00:00
mhitch dc1ece0234 Move the mips*_dump_tlb() routines outside the #ifdef so they are always
available.  Used in the locore ktlbmiss/panic to display the TLB contents
that are mapping the kernel stack.
1997-06-23 21:48:28 +00:00
mhitch f200f89fe7 Remove an incorrect store of the SP when displaying information about a
ktlbmiss on the kernel stack.  It was showing the temporary SP, not the
original SP.

Add a display of the first few wired entries of the TLB so when the ktblmiss
occurs, the TLB entries mapping the kernel stack can be verified.
1997-06-23 21:45:05 +00:00
jonathan 0d95f6f43d Align to 8-byte boundary after ASMSTR(), for mips3. 1997-06-23 06:15:28 +00:00
jonathan d2faa7a82b Set kernel text start address in port-specific Makefile, not ldscript. 1997-06-23 02:40:28 +00:00
jonathan 1eba6a6cc9 Disambiguate cache-size message, as suggested by cgd. 1997-06-22 12:22:37 +00:00
jonathan 1f44934407 * Change Sprite MACH_xxx prefix to MIPS_xxx.
* Use standard mips terminology (xxx_KSEG0, xxx_KSEG1) instead of the
  (more meaningful) Sprite names (xxx_CACHED, xxx_UNCACHED).
1997-06-22 07:42:25 +00:00
jonathan b86aa7f311 Fix typo mips3_mips_switch_exit. 1997-06-22 04:30:01 +00:00
jonathan 4692a37162 Final changes for configuring MIPS1 and MIPS3 in a single kernel.
* cpuregs.h:
    rename remaining VMMACH_xxx TLB macros to MIPS_TLB_xxx.
    Add compile-time MIPS3-only, compile-time  MIPS1-only, and
    runtime (both) definitions  for number of TLB ASIDs (tlb pids)
    and shift count to extract a TLB pid.

  * locore.h:
    Delete unused vector slot for indexed TLB writes.
    mips1 and mips3 TLBs are different enough that we have
    to break them out at the caller anyway.

  * Add compile-time MIPS3-only andcompile-time  MIPS1-only
    macros to call locore functions directly by name.
    Use the  existing method table only if

  * mips/mips_machdep.c, mips/trap.c, mips/pmap.c, pmax/machdep.c:
    Use MIPS3_ or MIPS1_ specific names for TLB pids in
    mips3 and mips1 specific code paths (e.g., creating the kernel stack
    for process 0).

Add `options MIPS3' to pmax/conf/GENERIC.
1997-06-22 03:17:37 +00:00
mhitch a7ac6e48ad Move the CPU-specific shift of the TLB PID into mips_r?000.S. 1997-06-21 06:32:22 +00:00
mhitch b027d98eb5 MachHitFlushDCache is gone. 1997-06-21 04:52:26 +00:00
mhitch edbde97cdf Fix pmap_prefer() to work in merged for mips1/mips3.
Remove unused debug procedure I forgot to remove previously.
Consolidate the vm_page_free1() calls in pmap_release().  Duplicate code
was a result of the way I merged the MIPS3 support from the pica pmap.c.
Enhance the comment on flushing the cache when releasing the segmap pages,
and add a comment about the currently unused code to uncache pages in
pmap_enter_pv().
1997-06-21 04:36:22 +00:00
mhitch 478559dd28 Merged mips1/mips3: cache alias test in pagemove(). 1997-06-21 04:24:45 +00:00
mhitch 51d10edcf2 Restore a lost (int) case in DELAYBRANCH macro - test for BR delay in
unsigned cause register wouldn't have worked.
Add missing ')' in trapdump that shows up when compiled with DEBUG.
Fix (unfix?) previous change to printf formats in mips3_dump_tlb: vad_to_pfn
is now consistant with single-CPU and merged-CPU support.
1997-06-21 04:18:29 +00:00
jonathan 68863ebd8e More mips1/mips3 changes to cpuregs.h and psl.h:
* cpuregs.h:
  Delete unused VMMACH_ names (e.g., duplicates of PTE bits in  pte.h).
  Change remaining VMMACH_xxx  names to MIPS1_xxx or MIPS3_xx.
  Fold remaining compile-time definitions into a single #ifdef MIPS3.

* Use MIPS1_ names  in locore_r2000.S, mips3_ names in locore_r4000.S

* Garbage-collect MachHitFlushDCache()

* psl.h:
  use MIPS1_, MIPS3_  symbolic names for Cause register bits.
  change  _R3K to MIPS1_,  _R4K to MIPS3. Conditionalize for mips1 only,
  mips3 only, or when both are defined,  use runtime CPUISMIPS3 test.
1997-06-21 04:18:09 +00:00
mhitch e03cf7a95c Cast mips1-only and mips3-only pfn_to_vad() macros to match the mips1/mips3
merged inline function.  Fixes inconsist printf format usage in trap.c.
1997-06-21 04:10:42 +00:00
jonathan 63b4439556 Correct cast type on mips3_MachHitFlushDCache(). 1997-06-20 07:35:03 +00:00
jonathan 5ed24fd4b4 trapDump(): compute accurate mask for EXC_CODE from CPU type at runtime. 1997-06-20 05:15:36 +00:00
jonathan c6c2263566 MachHitFlushDCache -> mips3_HitFlushDCache().
Add  XXX reminder to d-cache flush I don't understand.
1997-06-20 04:34:38 +00:00
mhitch 9b445e15ea Use same cachesize variables for mips1 and mips3, and rename the variables
per Jonathan's request.
Remove switch_exit() declaration - it's now called via the locore jump vector.
1997-06-19 06:34:16 +00:00
mhitch 4fa507b4fc More merged mips1/mips3 support:
Remove cpu-specific routines from locore.S and add them to locore_r2000.S
and locore_r4000.S.  Add entries in locore jump vector table for switch_exit()
and the cpu_switch() context resume.
Add offsets into the jump vector to genassym.cf for use in locore.S.
1997-06-19 06:31:14 +00:00